/TestThinpadProject

A simple PC model implementation and testbench using VHDL and Verilog.

Primary LanguageVHDL

Description

This project uses Vivado to implement a simple PC module in VHDL, and testbench in Verilog. The detailed information can be found in www.jianshu.com/p/fe70c57c20f4 。

Testbench Results

Simulation Result Small

Simulation Result Big

From the simulation results, we can see that the implementation is correct.