Pinned Repositories
basic_verilog
Must-have verilog systemverilog modules
CSI2Rx
Open Source 4k CSI-2 Rx core for Xilinx FPGAs
fusesoc
FuseSoC is a package manager and a set of build tools for FPGA/ASIC development
Hackster
Files used with hackster examples
icestorm
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
oh
Silicon proven Verilog library for IC and FPGA designers
pp4fpgas-cn
中文版 Parallel Programming for FPGAs
pp4fpgas-cn-hls
HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
PYNQ-Z2project
PYNQ-Z2工程
Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
zhangjialiang-tt's Repositories
zhangjialiang-tt/basic_verilog
Must-have verilog systemverilog modules
zhangjialiang-tt/CSI2Rx
Open Source 4k CSI-2 Rx core for Xilinx FPGAs
zhangjialiang-tt/fusesoc
FuseSoC is a package manager and a set of build tools for FPGA/ASIC development
zhangjialiang-tt/Hackster
Files used with hackster examples
zhangjialiang-tt/icestorm
Project IceStorm - Lattice iCE40 FPGAs Bitstream Documentaion (Reverse Engineered)
zhangjialiang-tt/oh
Silicon proven Verilog library for IC and FPGA designers
zhangjialiang-tt/pp4fpgas-cn
中文版 Parallel Programming for FPGAs
zhangjialiang-tt/pp4fpgas-cn-hls
HLS Project of pp4fpgas - https://github.com/xupsh/pp4fpgas-cn
zhangjialiang-tt/PYNQ-Z2project
PYNQ-Z2工程
zhangjialiang-tt/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
zhangjialiang-tt/ThinkDSP
Think DSP: Digital Signal Processing in Python, by Allen B. Downey.
zhangjialiang-tt/verilog
Repository for basic (and not so basic) Verilog blocks with high re-use potential
zhangjialiang-tt/verilog-axi
Verilog AXI components
zhangjialiang-tt/verilog-ethernet
Verilog Ethernet components
zhangjialiang-tt/Verilog_PAL
PAL时序的Verilog实现
zhangjialiang-tt/DSITx
MIPI DSI transmitter core for Xilinx FPGAs (work in progress)
zhangjialiang-tt/gen_amba_2021
AMBA bus generator including AXI4, AXI3, AHB, and APB
zhangjialiang-tt/GowinDDR3_AXI4_SpinalHDL
Gowin DDR3 Controller with AXI4 Implementation | 高云DDR3内存控制器AXI4接口实现
zhangjialiang-tt/hVHDL_fixed_point
VHDL library of high abstraction level synthesizable mathematical functions for multiplication, division and sin/cos functionalities and abc to dq transforms.
zhangjialiang-tt/PYNQ-Z2-Projects
zhangjialiang-tt/sdram-controller
Verilog SDRAM memory controller
zhangjialiang-tt/SpinalTemplateSbt
A basic SpinalHDL project
zhangjialiang-tt/verilog-axis
Verilog AXI stream components for FPGA implementation
zhangjialiang-tt/zhangjialiang-tt.github.io