A Pipelined CPU design, Quartus platform, Verilog HDL, Team Work
An implementation of a MIPS CPU written in Verilog. This project is in very early stages and currently only implements the most basic functionality of a MIPS CPU.
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32-bit MIPS processor
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implemented in Verilog
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5 stage pipeline
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static branch not taken branch predictor
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branch detection in decode (stage 2)
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supports stalls to avoid read after write (RAW) and other hazards
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can forward from memory (stage 4) and write back (stage 5)
This project requires a Verilog simulator, such as Quartus.
Rui-Yi Zhang zhangry868@126.com
http://github.com/zhangry868
Dong Xu
Qian-Ke Li
Copyright © 2014, Rui-Yi Zhang, Dong Xu, Qian-Ke Li. All Rights Reserved.
This project is free software and released under the GNU General Public License.