Pinned Repositories
Auto-GPT
An experimental open-source attempt to make GPT-4 fully autonomous.
awesome-python
A curated list of awesome Python frameworks, libraries, software and resources
bbr
BBR' - An Implementation of Bottleneck Bandwidth and Round-trip Time Congestion Control for ns-3
bpf_study
bpf 学习仓库
camctl
Mirror of the Icarus Camera Control project source
caribou
Caribou: Distributed Smart Storage built with FPGAs
chisel3
Chisel 3: A Modern Hardware Design Language
clash
A rule-based tunnel in Go.
cocotb-test
Unit testing for cocotb
corundum
Open source, high performance, FPGA-based NIC
zhangxiaoyu00's Repositories
zhangxiaoyu00/Auto-GPT
An experimental open-source attempt to make GPT-4 fully autonomous.
zhangxiaoyu00/bpf_study
bpf 学习仓库
zhangxiaoyu00/chisel3
Chisel 3: A Modern Hardware Design Language
zhangxiaoyu00/clash
A rule-based tunnel in Go.
zhangxiaoyu00/cocotb-test
Unit testing for cocotb
zhangxiaoyu00/DeepMosaics
Automatically remove the mosaics in images and videos, or add mosaics to them.
zhangxiaoyu00/FlooNoC
A Fast, Low-Overhead On-chip Network
zhangxiaoyu00/gen_apb_file
zhangxiaoyu00/iTerm2-zmodem
Automatic ZModem support for iTerm 2
zhangxiaoyu00/llama
Inference code for LLaMA models
zhangxiaoyu00/menshen
zhangxiaoyu00/MS-DOS
The original sources of MS-DOS 1.25, 2.0, and 4.0 for reference purposes
zhangxiaoyu00/open-rdma
RoCE v2 hardware implementation using Spinal HDL
zhangxiaoyu00/pigasus
100Gbps Intrusion Detection and Prevention System
zhangxiaoyu00/psp
zhangxiaoyu00/pspin
PsPIN: A RISC-V in-network accelerator for flexible high-performance low-power packet processing
zhangxiaoyu00/Pyverilog
Python-based Hardware Design Processing Toolkit for Verilog HDL
zhangxiaoyu00/qemu-hdl-cosim
VM-HDL Co-Simulation for Servers with PCIe-Connected FPGAs
zhangxiaoyu00/riscv-boom
SonicBOOM: The Berkeley Out-of-Order Machine
zhangxiaoyu00/RobustVideoMatting
Robust Video Matting in PyTorch, TensorFlow, TensorFlow.js, ONNX, CoreML!
zhangxiaoyu00/skywater-pdk
Open source process design kit for usage with SkyWater Technology Foundry's 130nm node.
zhangxiaoyu00/SpinalHDL
Scala based HDL
zhangxiaoyu00/sv-parser
SystemVerilog parser library fully complient with IEEE 1800-2017
zhangxiaoyu00/systemverilog-python
Systemverilog DPI-C call Python function
zhangxiaoyu00/UGATIT
Official Tensorflow implementation of U-GAT-IT: Unsupervised Generative Attentional Networks with Adaptive Layer-Instance Normalization for Image-to-Image Translation (ICLR 2020)
zhangxiaoyu00/v2ray_bin
梅林380 固件的魔改科学上网插件
zhangxiaoyu00/verilog-perl
Verilog parser, preprocessor, and related tools for the Verilog-Perl package
zhangxiaoyu00/virtio-fpga
A platform for emulating Virtio devices with FPGAs
zhangxiaoyu00/virtio-fpga-bridge
Virtio front-end and back-end bridge, implemented with FPGA.
zhangxiaoyu00/zcash-fpga
Zcash FPGA acceleration engine