zhaohui-ma

Pinned Repositories

oscpu-chisel-framework
Chisel development framework for OSCPU project
Language:Scala00
oscpu-framework
oscpu-framework
Language:Verilog00
SHA_SM3_SM4-Encryption-Algorithm
With basic SM3 & SM4 Encryption IP implemented with both Verilog and C , along with package for switching between SHA and SM3
Language:C00
SM4-SBOX
Verilog Implementation of SM4 s-box
Language:Verilog00
Trigger
RISC-V core designed by zyh in chisel language
10
XiangShan
Open-source high-performance RISC-V processor
Language:Scala00

zhaohui-ma's Repositories

zhaohui-ma/Trigger
RISC-V core designed by zyh in chisel language
10
zhaohui-ma/oscpu-chisel-framework
Chisel development framework for OSCPU project
Language:Scala00
zhaohui-ma/oscpu-framework
oscpu-framework
Language:Verilog00
zhaohui-ma/SHA_SM3_SM4-Encryption-Algorithm
With basic SM3 & SM4 Encryption IP implemented with both Verilog and C , along with package for switching between SHA and SM3
Language:C00
zhaohui-ma/SM4-SBOX
Verilog Implementation of SM4 s-box
Language:Verilog00
zhaohui-ma/XiangShan
Open-source high-performance RISC-V processor
Language:Scala00