- deadline: 12/12, 24:00 (5 days left)
- next meeting: this Fri, 16:00, at library b1 學習開放空間
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connect wires: 4 days # tue ddl
- stage1: PC, Add_pc, Instruction_Memory, IF/ID, flush, mux
- stage2: Control, Adder, Registers, Sign_Extend, hazardDetetion, eq, ID/EX
- stage3: ALU, ALU_Control, forwording, EX/MEM, mux
- stage4: data memory, MEM/WB
- stage5: mux
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test and debug: # Fri ddl
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write report (in Chinese): # Sun ddl
- part2: write about the stage(s) you implemented
- part3, 4: write about your own modules and problems
- Don't forget to upload your part of report as well
- Mind the consistency of names of variables