zhenyanjie/schedule

Schedule

Possible Direction

• Chisel
  • Scala
• Spike
• Heracles

Todo List

Item	Deadline	Status
Add memory bandwidth monitor for Spike	28 Jan
Read Privileged ISA spec v1.10	22 Jan
Port sv6 to RV64	25 Feb

Useful Links

• RISC-V
  • CNRV, RISC-V related news
  • RISC-V Specifications
  • RISC-V Software
  • RISC-V Cores
• PARD
  • paper link
  • PARD-gem5
  • labeled-RISC-V
• Chisel
  • Short Guide to Chisel In Chinese
  • Chisel Tutorial
  • A Scala Tutorial for Java programmers
• Heracles
  • paper link

Papers

• Supporting Differentiated Services in Computers via Programmable Architecture for Resourcing-on-Demand (PARD)
• Labeled RISC-V: A New Perspective on Software-Defined Architecture
• Heracles: Improving Resource Efficiency at Scale
• Locating Cache Performance Bottlenecks Using Data Profiling
• ZygOS: Achieving Low Tail Latency for Microsecond-scale Networked Tasks
• HDFI: Hardware-Assisted Data-flow Isolation
• A Virtual Instruction Set Interface for Operating System Kernels