zhewen404

University of Wisconsin-Madison

Pinned Repositories

UnarySim
This is a general-purpose simulator for unary computing based on PyTorch, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top Pick for 2020.
Language:SystemVerilog39 4 07
759Project
Language:Cuda0 1 00
booksim2
BookSim 2.0
Language:C++0 0 00
buffets
Implementations of Buffets, which are efficient, composable idioms for implementing Explicit Decoupled Data Orchestration.
Language:Verilog00
cache-profiling
Language:C++00
ChampSim
ChampSim repository
Language:C++00
condor
Language:Jupyter Notebook00
config
Language:Vim script00
gem5-resources
Language:C00
gem5tomcpat
Language:Python22

zhewen404's Repositories

zhewen404/gem5tomcpat
Language:Python22
zhewen404/759Project
Language:Cuda0 1 00
zhewen404/booksim2
BookSim 2.0
Language:C++0 0 00
zhewen404/cache-profiling
Language:C++00
zhewen404/ChampSim
ChampSim repository
Language:C++00
zhewen404/condor
Language:Jupyter Notebook00
zhewen404/config
Language:Vim script00
zhewen404/gem5-resources
Language:C00
zhewen404/hub_pe
Language:SystemVerilog01
zhewen404/gem5
Language:C++1
zhewen404/gem5-myfeature
Language:C++1
zhewen404/HieraGen
We present HieraGen, a new tool for automatically generating hierarchical cache coherence protocols. HieraGen's inputs are the simple, atomic, stable state protocols for each level of the hierarchy. HieraGen's output is a highly concurrent hierarchical protocol, in the form of the finite state machines for all of the cache and directory controllers. HieraGen thus reduces the complexity that architects face, by offloading the challenging tasks of composing protocols and managing concurrency. Experiments show that HieraGen can automatically generate correct-by-construction MOESI family of hierarchical protocols with dozens of states and hundreds of transitions. We have verified all of the generated protocols for safety and deadlock freedom using a model checker.
Language:Python0 0
zhewen404/HW_FC
Language:SystemVerilog
zhewen404/macsim
A heterogeneous architecture timing model simulator.
zhewen404/mirage
MIRAGE (USENIX Security 2021)
zhewen404/Murphi3.1
Language:C++1
zhewen404/nn_dataflow
Explore the energy-efficient dataflow scheduling for neural networks.
Language:Python0 0
zhewen404/noxim
Network on Chip Simulator
zhewen404/pin-3.24-98612-g6bd5931f2-gcc-linux
my pin tool repository
Language:C++
zhewen404/pycachesim
Python Cache Hierarchy Simulator
zhewen404/SCSim
Language:Python
zhewen404/submit
Language:Shell
zhewen404/swap
zhewen404/syn_script
Language:SystemVerilog
zhewen404/Tools
Language:Tcl
zhewen404/UnarySim
This is a PyTorch-based simulator for general unary computing, with the paper accepted to ISCA 2020 and awarded IEEE Micro Top Pick for 2020.
Language:Python0 0
zhewen404/uSystolic-Sim
A systolic array simulator for multi-cycle MACs and varying-byte words, with the paper accepted to HPCA 2022.
Language:C++
zhewen404/util
Language:SystemVerilog
zhewen404/zhewen404
Config files for my GitHub profile.
zhewen404/zhewen404.github.io