zhihang-tan

zhihang-tan's Stars

• drom/awesome-hdl

  Hardware Description Languages

  98397

• eugene-tarassov/vivado-risc-v

  Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

  Language:Tcl883198

• EPFL-LAP/fpga19-MOMS

  Language:VHDL134

• cad-polito-it/ase_riscv_gem5_sim

  RISCV Gem5 simulator flow for Architetture dei Sistemi di Elaborazione

  Language:Python112

• chatanywhere/GPT_API_free

  Free ChatGPT API Key，免费ChatGPT API，支持GPT4 API（免费），ChatGPT国内可用免费转发API，直连无需代理。可以搭配ChatBox等软件/插件使用，极大降低接口使用成本。国内即可无限制畅快聊天。

  Language:Python26.5k2k

• freechipsproject/chisel-bootcamp

  Generator Bootcamp Material: Learn Chisel the Right Way

  Language:Jupyter Notebook996280

• schoeberl/chisel-examples

  Chisel examples and code snippets

  Language:Tcl24079

• freecores/8051

  8051 core

  Language:Verilog9933

• DeathKing/Learning-SICP

  MIT视频公开课《计算机程序的构造和解释》中文化项目及课程学习资料搜集。

  Language:Ruby11.1k1.5k

• cnlohr/mini-rv32ima

  A tiny C header-only risc-v emulator.

  Language:C1.7k139

• riscv-collab/riscv-gnu-toolchain

  GNU toolchain for RISC-V, including GCC

  Language:C3.7k1.2k

• riscv-collab/riscv-openocd

  Fork of OpenOCD that has RISC-V support

  Language:C458335

• KindXiaoming/pykan

  Kolmogorov Arnold Networks

  Language:Jupyter Notebook15.3k1.4k

• adam-maj/tiny-gpu

  A minimal GPU design in Verilog to learn how GPUs work from the ground up

  Language:SystemVerilog7.3k553

• OSCPU/yosys-sta

  Language:Verilog4810

• ucb-bar/riscv-mini

  Simple RISC-V 3-stage Pipeline in Chisel

  Language:Scala554114

• Kevincoooool/KS_DAP_Wireless

  STM32F103C8T6 无线有线DAP下载器，脱机（离线）烧录器，脱机下载器

  Language:C492191

• Kevincoooool/2018-NXP-CUIT-WD

  第十三届全国大学生恩智浦杯智能汽车竞赛 电磁直立组 成都信息工程大学 成信WD队

  Language:C7621

• espressif/esp-idf

  Espressif IoT Development Framework. Official development framework for Espressif SoCs.

  Language:C14.2k7.4k

• riscv-non-isa/riscv-arch-test

  Language:Assembly527209

• riscv-software-src/riscv-tests

  Language:C919473

• shinezyy/micro-arch-training

  How to make undergraduates or new graduates ready for advanced computer architecture research or modern CPU design

  49439

• grantae/OpenMIPS

  A full implementation of the MIPS32 Release 1 ISA, including virtual memory, TLB, instruction and data caches, interrupts and exceptions, over 100 hw/sw tests, and full ISA compliance

  Language:Assembly6514

• TouchFishPioneer/SEU-master-thesis

  东南大学硕士研究生学位论文LaTeX模板

  Language:TeX17242

• xinychen/latex-cookbook

  LaTeX论文写作教程 (清华大学出版社)

  Language:Jupyter Notebook1.4k152

• ucb-bar/riscv-sodor

  educational microarchitectures for risc-v isa

  Language:Scala694155

• ultraembedded/biriscv

  32-bit Superscalar RISC-V CPU

  Language:Verilog904151

• riscv-mcu/e203_hbirdv2

  The Ultra-Low Power RISC-V Core

  Language:Verilog1.4k348

• liangkangnan/tinyriscv

  A very simple and easy to understand RISC-V core.

  Language:C1.1k192

• olofk/serv

  SERV - The SErial RISC-V CPU

  Language:Verilog1.5k193