zhuanshulz

Pinned Repositories

7002_opt
Language:Assembly0 0 00
arm-gem5-rsk
Official repository of the Arm Research Starter Kit on System Modeling using gem5
Language:Shell0 0 00
BMP_IMAGE_READER
Language:C0 1 00
cbp2016
Language:C++1 1 10
CVP
Championship Value Prediction (CVP) simulator.
Language:C++0 0 00
EVES_DSE
Language:C++0 1 00
mul_RV32I
Using RISCV Integer Instruction Set to Finish Unsigned Multiplication Operation.
Language:C0 1 00
PGL22G_SOC_Platform
Language:C3 0 00
RV32_chisel
基于chisel语言编写的RISCV微处理器核，仅支持RV32I指令级，无特权级。
Language:C2 1 00
RV32I_X
Language:C0 1 00

zhuanshulz's Repositories

zhuanshulz/PGL22G_SOC_Platform
Language:C3 0 00
zhuanshulz/RV32_chisel
基于chisel语言编写的RISCV微处理器核，仅支持RV32I指令级，无特权级。
Language:C2 1 00
zhuanshulz/cbp2016
Language:C++1 1 10
zhuanshulz/7002_opt
Language:Assembly0 0 00
zhuanshulz/arm-gem5-rsk
Official repository of the Arm Research Starter Kit on System Modeling using gem5
Language:Shell0 0 00
zhuanshulz/BMP_IMAGE_READER
Language:C0 1 00
zhuanshulz/CVP
Championship Value Prediction (CVP) simulator.
Language:C++0 0 00
zhuanshulz/EVES_DSE
Language:C++0 1 00
zhuanshulz/mul_RV32I
Using RISCV Integer Instruction Set to Finish Unsigned Multiplication Operation.
Language:C0 1 00
zhuanshulz/RV32I_X
Language:C0 1 00
zhuanshulz/fina_atheletes
Language:Python0 0
zhuanshulz/gem5-changes
Version control to continue editting gem5 while testing on SPEC2017 benchmarks
Language:C++0 0
zhuanshulz/hls4ml
Machine learning in FPGAs using HLS
Language:C++0 0
zhuanshulz/open-box
Generalized and Efficient Blackbox Optimization System [SIGKDD'21].
Language:Python0 0
zhuanshulz/riscv-vectorized-benchmark-suite
RiVEC Bencmark Suite
Language:C++0 0
zhuanshulz/zhuanshulz
Config files for my GitHub profile.
1 0
zhuanshulz/zhuanshulz.github.io
Language:HTML1 0