zjzkff

Pinned Repositories

• AccDNN

  A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.

  Language:Verilog00

• Accelerating-CNN-with-FPGA

  This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.

  Language:C++00

• azpr_cpu

  用Altera FPGA芯片自制CPU

  Language:Verilog00

• BARVINN

  BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/

  Language:Tcl0000

• bigpulp

  ⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform

  Language:SystemVerilog0000

• bilinear

  Bilinear interpolation realizes image scaling based on FPGA

  Language:Verilog00

• chipyard

  An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more

  Language:C0000

• CNN-ACCELERATOR

  Hardware accelerator for convolutional neural networks

  Language:Verilog1000

• CNN-Accelerator-VLSI

  Convolutional accelerator kernel, target ASIC & FPGA

  Language:Verilog0000

• Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA

  Verilog Generator of Neural Net Digit Detector for FPGA

  Language:Verilog1000

zjzkff's Repositories