Pinned Repositories
AccDNN
A compiler from AI model to RTL (Verilog) accelerator in FPGA hardware with auto design space exploration.
Accelerating-CNN-with-FPGA
This project accelerates CNN computation with the help of FPGA, for more than 50x speed-up compared with CPU.
azpr_cpu
用Altera FPGA芯片自制CPU
BARVINN
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
bigpulp
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
bilinear
Bilinear interpolation realizes image scaling based on FPGA
chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
CNN-ACCELERATOR
Hardware accelerator for convolutional neural networks
CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA
Verilog Generator of Neural Net Digit Detector for FPGA
zjzkff's Repositories
zjzkff/CNN-ACCELERATOR
Hardware accelerator for convolutional neural networks
zjzkff/Verilog-Generator-of-Neural-Net-Digit-Detector-for-FPGA
Verilog Generator of Neural Net Digit Detector for FPGA
zjzkff/BARVINN
BARVINN: A Barrel RISC-V Neural Network Accelerator: https://barvinn.readthedocs.io/en/latest/
zjzkff/bigpulp
⛔ DEPRECATED ⛔ RISC-V manycore accelerator for HERO, bigPULP hardware platform
zjzkff/chipyard
An Agile RISC-V SoC Design Framework with in-order cores, out-of-order cores, accelerators, and more
zjzkff/CNN-Accelerator-VLSI
Convolutional accelerator kernel, target ASIC & FPGA
zjzkff/DES_Hardware_Accelerator
Hardware acceleration combines the flexibility of general-purpose processors, such as CPUs, with the efficiency of fully customized hardware, such as GPUs and ASICs, increasing efficiency by orders of magnitude when any application is implemented higher up the hierarchy of digital computing systems
zjzkff/DetectHumanFaces
Real time face detection based on Arm Cortex-M3 DesignStart and FPGA
zjzkff/e200_opensource
Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2
zjzkff/e203_hbirdv2
The Ultra-Low Power RISC-V Core
zjzkff/fadec
zjzkff/FPGA-proj
FPGA project
zjzkff/FPGA-stereo-Camera-Basys3
Integration of two camera modules to Basys 3 FPGA
zjzkff/FPGAandCNN
基于FPGA的数字识别-实时视频处理的定点卷积神经网络实现
zjzkff/GNN-ARCH
[ASAP 2020; FPGA 2020] Hardware architecture to accelerate GNNs (common IP modules for minibatch training and full batch inference)
zjzkff/Hand-Writing-Digital-Recognization-Based-on-FPGA
Hand Writing Digital Recognization Based on FPGA, we desiged a SoC embeded a Cortex M3 core and other peripherals，this SoC run a CNN. The SoC worked not bad in the end the success rate up to 90%。.
zjzkff/Hardware-Accelerated-Video-Compression-using-DCT
Individual Contributions to my team's CPEN 391 final project. I developed the video frame capture system for the D8M, created Avalon slaves for hardware-software interfacing and the DCT hardware accelerator
zjzkff/hero
Heterogeneous Research Platform (HERO) for exploration of heterogeneous computers consisting of programmable many-core accelerators and an application-class host CPU, including full-stack software and hardware.
zjzkff/ImageStitchBasedOnFPGA
七路图像在FPGA中实现拼接，代码会不断添加进来。
zjzkff/MVU
Neural Network accelerator powered by MVUs and RISC-V.
zjzkff/NutShellTeam
果壳处理器研究小组(Topic:基于RISCV64果核处理器的卷积神经网络加速器研究)
zjzkff/pito_riscv
A Barrel design of RV32I
zjzkff/tinyriscv
A very simple and easy to understand RISC-V core.
zjzkff/USTC-RVSoC
An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V CPU+SoC，包含一个简单且可扩展的外设总线。
zjzkff/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
zjzkff/wujian100_open
IC design and development should be faster，simpler and more reliable
zjzkff/XS-Verilog-Library
除法器
zjzkff/yolov2_xilinx_fpga
A demo for accelerating YOLOv2 in xilinx's fpga pynq/zedboard
zjzkff/zjzkff
Config files for my GitHub profile.
zjzkff/zjzkff.github.io