An accumulator based 16 bit three stage parallel processor (work in progress).
##Background
The Karpentium Processor began as a semester project for EE685 Digital Computer Structure at the University of Kentucky. With a continued interest in the topic, I've expanded the project adding more features, replacing inefficent code and optimizing my design.
Karpentium is not complete and is still a work in progress. Here is a list of known issues:
- Not all features from the original design are implemented
Coming Soon...
- Migen - Library used for the Python3 implementation.
- GTKwave - Opensorce Waveform viewer.
- Xilinx - The intial design, verification, implementation and testing platform.
With many projects I do, I try to incorporate my nickname and online handle, 'Karp', with them. When studying the early IBM processors, I jokingly said I would design a competing processor with IBM named the Karpentium Processor. The name has stuck since.