zslwyuan/AMF-Placer

Issues

• Can i have the original design and device file of the VCU108?

  #13 opened 8 months ago by BQ233
  1

• can't reach patoh-Linux-x86_64.tar.gz

  #11 opened a year ago by SivanLaai
  2

• Could not find "Q_WS_WIN", "Q_WS_QWS" and "Q_WS_MAC" during the cmake

  #10 opened a year ago by tomqingo
  1

• Legalization bugs when cells in a macro are placed across clock region

  #6 opened 2 years ago by zslwyuan
  1

• Timing-driven FPGA Placement enabled

  #9 opened 2 years ago by zslwyuan
  1

• WARNING: We are integrating the timing-driven functions and it might lead to unstable problems of benchmark "OptimSoC"

  #5 opened 2 years ago by zslwyuan
  2

• Extension to other Xilinx FPGA device

  #8 opened 2 years ago by lesliepy99
  5

• Please don't hesitate to contact us if you encounter problems with our AMF-Placer

  #7 opened 3 years ago by zslwyuan
  0

• SLR/Clock/Congestion-Aware Initial Placement

  #1 opened 3 years ago by zslwyuan
  0

• After introducing timing optimization, some half-column clock regions get legalization violation (will be solved soon)

  #4 opened 3 years ago by zslwyuan
  1

• reorganize the architecture of the placer and make processors act like LLVM passes(TODO)

  #3 opened 3 years ago by zslwyuan
  1