/MIPS-CPU

Implement a MIPS CPU from both software and hardware perspectives. [Get 100/100]

Primary LanguageVerilogMIT LicenseMIT

MIPS-CPU

HUST Computer Organization Course Design 2019.2

Implement a MIPS CPU from both software and hardware perspectives.

Environment

  • Software:
    • logisim
  • Hardware:
    • Verilog HDL
    • FPGA

Features

  • Five-stage pipeline
  • Support 28 instructions
  • Support redirection
  • Support dynamic branch prediction
  • Support multi-stage pipeline interrupt

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