zzabR

zzabR's Stars

• lucky-wfw/ARM_AMBA_Design

  Based on ARM AMBA bus protocol, Verilog is used to design the digital circuit.

  Language:Verilog11334

• KasuganoSoraaa/simple-AXI2AHB-bridge

  AXI master to AHB slave, support INCR/WRAP, out of standing, do not advanced feature such as support out of order, retry, split, etc

  Language:Verilog3311

• NikolaF-95/RAM_VIP

  UVM VIP for Single Port RAM Synchronous Read/Write

  Language:SystemVerilog51

• Shehab-Naga/ddr5_phy

  DDR5 PHY Graduation project (Verification Team) under supervision of Si-Vision

  Language:SystemVerilog4222

• dadongshangu/async_FIFO

  This asynchrounous FIFO deisgn and UVM verificaiton is one case study of me. The design is based on Cliff Cumming's paper and the UVM is coded by me(Xianghzi Meng)

  Language:SystemVerilog5515

• kumarrishav14/AXI

  VIP for AXI Protocol

  Language:SystemVerilog11835

• taichi-ishitani/tvip-axi

  AMBA AXI VIP

  Language:SystemVerilog366106

• nguyenquanicd/UvmEnvUartApb

  This is the UVM environment for UART-APB IP core. This environment contains full UVM components. It is only used for studing and invetigating the UVM env.

  Language:SystemVerilog184

• hanysalah/uart2bustestbench

  UVM Verification IP to uart2bus IP.

  Language:SystemVerilog217

• alexforencich/verilog-pcie

  Verilog PCI express components

  Language:Verilog1.2k305