SPI Verilog modules 2 SPI implementations:
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Fully Hard for FPGA without CPU core like Spartan 6 or Cyclone 4, e.t.c. features:
- setting bit (MSB, LSB) and bytes order (Little endian or Big endina)
- adjustable number of extra clocks when some devices needs to make internal synchronizzation while CS is still active and clock keep going from clk (Dragster/Awaiba/Cmosis DR-2k-7)
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Fully soft SPI with AXI Full interface with CPU.