/Single-Cycle-16-Bit-MIPS

Only Does R-Type Instruction of add,sub,and,or And I-Type Instruction of lw,sw

Primary LanguageVerilog

Single-Cycle-16-Bit-MIPS

Complex Engineering Problem (CEP) By:

Osama Anees, Rayyan Munir and Muneeb Khan.

Only Does R-Type Instruction of add,sub,and,or And I-Type Instruction of lw,sw,addi. Also does J-Type Instruction of JUMP.

How to compile it?

Download

Compile

  1. Open the Single_Cycle_Top_tb.v file. Make sure to edit your "includes" file path in the test bench and Single_Cycle_Top.v file.
  2. Go to terminal and type:
  • iverilog Single_Cycle_Top_tb.v
    • This will generate an "a.out" file.
  • vvp a.out
    • This will convert the .out file into vcd file which gtkwave can read.
  • gtkwave Single_Cycle.vcd
    • GTKWave will open the wave file.
    • To make groups press "Ctrl+B" to create a blank block. Then press "G" to create a group. Just insert things in it.

Generated by TerosHDL © 2020-2021 License GPLv3
Carlos Alberto Ruiz Naranjo (carlosruiznaranjo@gmail.com)
Ismael Perez Rojo (ismaelprojo@gmail.com)

Project revision 2023-06-20 01:25:05

system

Designs

Please see 6th_Semester_COAL_CEP.pdf for further information.

Special Thanks To MERL_DSU Who Created The Youtube Playlist For Single_Cycle_RISC_Core: