Complex Engineering Problem (CEP) By:
Osama Anees, Rayyan Munir and Muneeb Khan.
Only Does R-Type Instruction of add,sub,and,or And I-Type Instruction of lw,sw,addi. Also does J-Type Instruction of JUMP.
- Icarus Verilog: https://github.com/steveicarus/iverilog
- VS-Code: https://code.visualstudio.com/
- Xilinx ISE: https://www.xilinx.com/products/design-tools/ise-design-suite/ise-webpack.html
- GTKWave: https://gtkwave.sourceforge.net/
- Open the Single_Cycle_Top_tb.v file. Make sure to edit your "includes" file path in the test bench and Single_Cycle_Top.v file.
- Go to terminal and type:
- iverilog Single_Cycle_Top_tb.v
- This will generate an "a.out" file.
- vvp a.out
- This will convert the .out file into vcd file which gtkwave can read.
- gtkwave Single_Cycle.vcd
- GTKWave will open the wave file.
- To make groups press "Ctrl+B" to create a blank block. Then press "G" to create a group. Just insert things in it.
Generated by TerosHDL © 2020-2021 License GPLv3
Carlos Alberto Ruiz Naranjo (carlosruiznaranjo@gmail.com)
Ismael Perez Rojo (ismaelprojo@gmail.com)
Project revision 2023-06-20 01:25:05
- Module: Sign_Extend
- Module: Reg_File
- Module: PC
- Module: PC_Adder
- Module: Mux
- Module: Instr_Mem
- Module: Data_Mem
- Module: control_unit
- Module: alu_control
- Module: alu
- Module: Single_Cycle_Top