1391074994/Verilog-Hdl-Format

Issues

• 变量名补全时无法识别到模块接口信号

  #3 opened 2 months ago by qiQWQwww
  1

• output reg

  #2 opened 6 months ago by rickformorty
  0

• 用户变量名补全失效 User variable name autocomplete not working

  #1 opened 7 months ago by qiQWQwww
  5