Pinned Repositories
AXI4_Interconnect
AXI总线连接器
AXI4_Master_Interconnect_Slave
A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.
axi_interconnect
AXI4 Interconnect
axi_soc
axi soc
C906_Gensys2
c906 soc
rocket-chip
Rocket Chip Generator
swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
zqh_riscv
zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this project Now it's focusing on Embedded system
ventus-gpgpu
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
1997xu's Repositories
1997xu/AXI4_Master_Interconnect_Slave
A generic implementation of AMBA AXI4 communication protocol. The design provides a master, a slave and an interconnect with multiple masters arbitration. Simulation waveforms are also included.
1997xu/axi_interconnect
AXI4 Interconnect
1997xu/C906_Gensys2
c906 soc
1997xu/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
1997xu/AXI4_Interconnect
AXI总线连接器
1997xu/axi_soc
axi soc
1997xu/rocket-chip
Rocket Chip Generator
1997xu/swerv_eh1
A directory of Western Digital’s RISC-V SweRV Cores
1997xu/zqh_riscv
zqh_riscv is an open source SOC system based on riscv core and tilelink NOC bus. coding with PHGL language(python DSL language). this project Now it's focusing on Embedded system