THU-DSP-LAB/ventus-gpgpu
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
ScalaMulanPSL-2.0
Issues
- 1
请问能否详细描述一下opencl和gpu的关系
#66 opened by c4midori - 4
verilator仿真波形为空
#67 opened by xiaokaijia1988 - 4
- 1
承影有SIMT-STACK的退栈指令吗?
#60 opened by ByeBeihai - 1
【RFC】关于ventus的gnu工具链支持
#29 opened by TuringKi - 1
- 1
生成Verilog时出现的问题
#49 opened by 1997xu - 2
How to generate .data file
#55 opened by RichardRo - 1
Where can I configure the number of cores?
#24 opened by MWHYNOT - 3
Chisel 3.6+ Support
#31 opened by sequencer - 2
你好,请问当前版本实现了MMU了吗?
#11 opened by eniacL - 4
fpga_test support and documentation
#52 opened by kmzaja - 1
make verilog编译报错:1 targets failed
#12 opened by eniacL - 2
关于承影的正确性验证
#46 opened by ByeBeihai - 5
make verilog编译报错
#19 opened by MWHYNOT - 1
- 4
saxpy2 test error
#33 opened by xiaoyu1004 - 0
- 2
- 11
support FPGA?
#21 opened by MWHYNOT - 1
When we use command "make compile", here report the following errors: val config = chipsalliance.rocketchip.config
#23 opened by bigdot123456 - 1
When run make test, it occur with the following message. Mill version is 0.10.8.
#22 opened by bigdot123456 - 0
make tests出错
#20 opened by MWHYNOT - 2
Environment setting for ventus
#10 opened by zhangliang1997 - 2
- 2
hello_test2 in ventus/tests/src/tests.scala
#8 opened by wuliJerry - 6
CUDA中的三维网格、线程块如何映射到硬件?
#2 opened by kaitoukito - 1
SIMT-deadlock
#1 opened by rill-zhen