Pinned Repositories
accel-sim-framework
This is the top-level repository for the Accel-Sim framework.
awesome-courses
:books: List of awesome university courses for learning Computer Science!
berkeley-cs61c
chisel-aes
Chisel implementation of AES
chiselv-test
A RISC-V Core (RV32I) written in Chisel HDL
digilent-xdc
A collection of Master XDC files for Digilent FPGA and Zynq boards.
EE290-2
gpgpu-optimized
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
matrix_mul_tb
xv6-lab
wuliJerry's Repositories
wuliJerry/gpgpu-optimized
GPGPU processor supporting RISCV-V extension, developed with Chisel HDL
wuliJerry/matrix_mul_tb
wuliJerry/xv6-lab
wuliJerry/accel-sim-framework
This is the top-level repository for the Accel-Sim framework.
wuliJerry/berkeley-cs61c
wuliJerry/chisel-aes
Chisel implementation of AES
wuliJerry/chiselv-test
A RISC-V Core (RV32I) written in Chisel HDL
wuliJerry/digilent-xdc
A collection of Master XDC files for Digilent FPGA and Zynq boards.
wuliJerry/EE290-2
wuliJerry/flash-attention
Fast and memory-efficient exact attention
wuliJerry/FlexFlow
A distributed deep learning framework.
wuliJerry/FlexGen
wuliJerry/fly
wuliJerry/fused_ckpt
wuliJerry/MatmulSprint
wuliJerry/my-nvim-config
wuliJerry/my_pre
wuliJerry/old_page
wuliJerry/ostep-projects
Projects for an undergraduate OS course
wuliJerry/saving-gv
wuliJerry/specinfer_prof
wuliJerry/ss
wuliJerry/v2ray-core
A platform for building proxies to bypass network restrictions.
wuliJerry/v2rayA
A web GUI client of Project V which supports VMess, VLESS, SS, SSR, Trojan, Tuic and Juicity protocols. 🚀
wuliJerry/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
wuliJerry/vitae
wuliJerry/vta-distro
A repository to cache VTA bistreams
wuliJerry/wuliJerry
Config files for my GitHub profile.
wuliJerry/yosys
Yosys Open SYnthesis Suite
wuliJerry/Yosys-script