ARH-23

ARH-23's Stars

• srsran/srsRAN_4G

  Open source SDR 4G software suite from Software Radio Systems (SRS) https://docs.srsran.com/projects/4g

  Language:C++3.5k2451k1.1k

• claimed-framework/component-library

  The goal of CLAIMED is to enable low-code/no-code rapid prototyping style programming to seamlessly CI/CD into production.

  Language:Jupyter Notebook2.3k88484.1k

• ika-rwth-aachen/acdc

  Code Repository for the MOOC "Automated and Connected Driving Challenges" available on edX.

  Language:C++16981123

• wchill/HMP_Dataset

  Language:Python714094

• chauhannaman98/edX-financial-assistance-answers

  422024

• codeamt/IBM-Advanced-Data-Science

  Notebooks from IBM Advanced Data Science Specialization. Topics include Scalable Data Science and Machine Learning for Signal Processing.

  Language:Jupyter Notebook264142

• abdelazeem201/ASIC-implementation-of-AES

  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The Verilog language is utilized for simulating the design and an fpga & ASIC chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput, and critical path delay.

  Language:Verilog18103

• ashishpatel26/Advanced-Machine-Learning-and-Signal-Processing-IBM

  Advanced Machine Learning and Signal Processing IBM

  Language:Jupyter Notebook166020

• HassanShafiq/Embedded-Systems

  This repository contains my coding implementations for Udemy based Embedded Systems and RTOS courses.

  Language:HTML11405

• mgraczyk/coursera-vlsicad

  Programming assignments for Coursera's U of I VLSI CAD: Logic to Layout

  Language:Python10305

• chisyliu/Sensor-Fusion-and-Nonlinear-Filtering-SSY345

  Repository for the course "Sensor Fusion and Non-Linear Filtering" - SSY345 at Chalmers University of Technology

  Language:MATLAB91020

• iadi7ya/Coursera

  This repository contains different Coursera Specilazation Assignment Solutions in Deep Learning, Big Data, Machine Learning and Data Science

  Language:Jupyter Notebook8319

• Mayakshanesht/PythonRobotics

  Python sample codes for robotics algorithms.

  Language:Python6001

• AlexGeControl/Emerging-Automotive-Technologies

  Workspace for ChalmersX's Emerging Automotive Technologies MicroMaster from edX

  Language:MATLAB3201

• jajoosiddhant/Advanced-Embedded-Software-Development-AESD

  Consists of Projects and Assignments Completed in Advanced Embedded Software Development Course | ECEN 5013-002 | University of Colorado, Boulder: System Calls, Kernel Modules, Cross-Compiling using buildroot, IPCs, FreeRTOS, Multithreading..

  Language:C3100

• suryajayaraman/SFNLF-edX

  Repo for Sensor Fusion and Non linear filtering course from Chalmers University, edX

  Language:MATLAB3102

• vertz/vlsicad

  VLSI CAD: Logic to Layout

  Language:C++3200

• niketanpansare/systemml

  Mirror of Apache SystemML

  Language:Java2301

• Abdelrahman350/Sensor_Fusion_and_Bayseian_Filtering

  Language:MATLAB1100

• ARH-23/ASIC-implementation-of-AES

  Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The Verilog language is utilized for simulating the design and an fpga & ASIC chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput, and critical path delay.

  Language:Verilog1100

• ARH-23/verilog-AES-encryption-decryption-128bit

  Language:Verilog1100

• AyushRajSharma/Hardware_AES_Algorithm

  AES Algorithm written in verilog for 128 bits key hardware simulation

  Language:Verilog1300

• benspniz/Advanced-Data-Science-with-IBM-Specialization

  Course work from Advanced Data Science with IBM Specialization

  Language:Jupyter Notebook1101

• chauhannaman98/DS-and-Algo

  A repository of C/C++ programs of data structures and algorithms

  Language:C++1230

• KevinLikesDringCoffe/FPGA-AES-encryptor

  AES processor impelmented by Verilog. This processor can run at the frequency of 100MHz and take 10 cycles to encrypt an 128-bit plain text.The processor uses several simple commands and state bits to input, encrypt and output the data.

  Language:Verilog1200

• Maginal336/verilog-AES-encryption-decryption-128bit

  Language:Verilog1201

• Nishanthravula/Xamarin_assignments

  1201

• Rajput616/SecondAssignmentWithSlider

  Language:C#110

• sserega9/Linux-System-Programming-and-Introduction-to-Buildroot

  Language:Shell110

• Yahya-Ashraf-Mohamed/Linux-System-Programming-and-Introduction-to-Buildroot

  Language:Shell1100