ARH-23

absolute-assignment

Advanced-Machine-Learning-and-Signal-Processing-IBM

Advanced Machine Learning and Signal Processing IBM

AES-128-decryption-using-Verilog

designing hardware using Verilog to decrypt AES message and implement the design with less than 3% of zynq FPGA resources in one-lab CU competition

AES-algorithm-verilog

AES-Processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

AES128

C++ and Verilog to implement AES128

ASIC-implementation-of-AES

Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The Verilog language is utilized for simulating the design and an fpga & ASIC chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput, and critical path delay.

assignment-1

c-ninja-listings

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

verilog-AES-encryption-decryption-128bit

ARH-23/AES-algorithm-verilog

ARH-23/AES128

C++ and Verilog to implement AES128

ARH-23/ASIC-implementation-of-AES

Advanced encryption standard (AES) algorithm has been widely deployed in cryptographic applications. This work proposes a low power and high throughput implementation of AES algorithm using key expansion approach. We minimize the power consumption and critical path delay using the proposed high performance architecture. It supports both encryption and decryption using 256-bit keys with a throughput of 0.06 Gbps. The Verilog language is utilized for simulating the design and an fpga & ASIC chip has been used for the hardware implementations. Experimental results reveal that the proposed AES architectures offer superior performance than the existing VLSI architectures in terms of power, throughput, and critical path delay.

ARH-23/verilog-AES-encryption-decryption-128bit

ARH-23/absolute-assignment

ARH-23/Advanced-Machine-Learning-and-Signal-Processing-IBM

Advanced Machine Learning and Signal Processing IBM

ARH-23/AES-128-decryption-using-Verilog

designing hardware using Verilog to decrypt AES message and implement the design with less than 3% of zynq FPGA resources in one-lab CU competition

ARH-23/AES-Processor

AES crypto engine written in System Verilog and emulated on the Mentor Veloce. First place winner of Mentor Graphics Need For Speed Emulation Competition 2016.

ARH-23/assignment-1

ARH-23/c-ninja-listings

Lower level assembly and C baremetal programming on RISC-V CPUs. Source code listings from the C-Ninja, in Pyjama! book.

ARH-23/Coursera

This repository contains different Coursera Specilazation Assignment Solutions in Deep Learning, Big Data, Machine Learning and Data Science

ARH-23/coursera-1

ARH-23/coursera-test

coursera test repository

ARH-23/fullstack-course4

Example code for HTML, CSS, and Javascript for Web Developers Coursera Course

ARH-23/grid-exercise-1-

ARH-23/grid-exercise-2-

ARH-23/IBM-Advanced-Data-Science

Notebooks from IBM Advanced Data Science Specialization. Topics include Scalable Data Science and Machine Learning for Signal Processing.

ARH-23/RelativeLayout

ARH-23/slider

ARH-23/Xamarin_assignments