AUCOHL/Lighter

Issues

• Update Reports to include $SDFFE cells

  #17 opened a year ago by kanndil
  0

• Fix all platforms' map files

  #19 opened a year ago by kanndil
  0

• SDFFE mapping crashes validation

  #2 opened a year ago by kanndil
  2

• Add liberty file for GF180 PDK

  #13 opened a year ago by kanndil
  2

• can i try this in openlane's yosys.

  #15 opened a year ago by Vinayakamk
  9

• Incorporate Lighter into OpenLane.

  #8 opened 2 years ago by kanndil
  0

• Move module to be part of yosys-f4pga-plugins

  #9 opened a year ago by mithro
  5

• Add support for other open source PDKs.

  #7 opened 2 years ago by kanndil
  2

• Make the plugin selection for both techmap and memory commands

  #12 opened 2 years ago by kanndil
  1

• Power report does not consider clock-gating cells high activity

  #5 opened 2 years ago by kanndil
  4

• Make lighter PDK independent

  #3 opened 2 years ago by kanndil
  1

• report_power.py needs to be generic

  #10 opened 2 years ago by kanndil
  1

• Move power_report_summary.csv from the root to a subfolder

  #11 opened 2 years ago by shalan
  1

• Add support for other sky130 standard cell libraries.

  #6 opened 2 years ago by kanndil
  1

• Blake2s_core clock gated design fails in validation

  #1 opened 2 years ago by kanndil
  1