Pinned Repositories
riscv-gnu-toolchain
GNU toolchain for RISC-V, including GCC
riscv-isa-sim
Spike, a RISC-V ISA Simulator
riscv-tests
riscv-isa-manual
RISC-V Instruction Set Manual
riscv-opcodes
RISC-V Opcodes
OpenLane
OpenLane is an automated RTL to GDSII flow based on several components including OpenROAD, Yosys, Magic, Netgen and custom methodology scripts for design exploration and optimization.
8bitcpu
my demo project
bitmanip-test
This simple lines of code could test the bit manipulation instructions.
riscv-config
RISC-V Configuration Validator
z3
The Z3 Theorem Prover
Vinayakamk's Repositories
Vinayakamk/8bitcpu
my demo project
Vinayakamk/bitmanip-test
This simple lines of code could test the bit manipulation instructions.
Vinayakamk/riscv-config
RISC-V Configuration Validator