University of British Columbia
Isabelle Andre
A series of labs on relevant and state of the art computer architecture topics using System Verilog
- Project 1 DNS Lookup Verilog FSM
- Project 2 Synthesized Verilog Project
- Project 3 MOS Transistor & Cadence
- Project 4 NAND3 Layout & Logic Function
- Project 5 Place and Route Domino Logic
This project consisted in creating a custom finite state machine in system verilog and a testbench to verify its design. As freedom of topic for this project was given, an FSM depicting the process of a complete DNS lookup and Webpage Query was created. This state machine contains 13 states, including the multiple stages of recursive and iterative queries between different data servers. Depending on the web address queried from the client, an address may be mapped to its corresponding IP address and cached in the browser for future usage, decreasing the total execution time of the lookup process.
This project consisted in using Cadence Encounter RTL Compiler to generate a mapped netlist based on a provided library of cells. The same DNS Lookup System Verilog FSM from Assignment 1 was used to create a netlist. The total number of cells and time slack of this FSM was generated by the RTL Compiler, and the generated graphical waves of the mapped Verilog file were compared to the initial waveforms from Assignment 1 to observe timing similarities and functioning.
A series of transistor simulations and analysis relating to inverter capacitance and propagation delays.
This project consisted in using the Cadence Design tools to layout and characterize a NAND3 circuit. First, the sizing of the transistors of the NAND3 gate are calculated using theoretical inverter sizing. A layout is then created, verifying the design using DRC, LVS, then extracting the parasitic components from the layout. The layout was designed with the aim of reducing the time delay and area as much as possible. Next, a logic circuit is analyzed and simulated to find its worst case rising and falling delays. Finally, the RC and Elmore delays for a transmission gates circuit are calculated, and optimized by deriving an optimal output inverter size.
This project consisted in using the Cadence Design tools to synthesize a Verilog DNSLookup state machine previously designed in Project 1 using a GPDK 45nm standard cell library. The synthesized design is then laid out and verified using the Cadence Innovus tool by auto-routing. In the next part of this project, domino logic is explored by determining voltage reduction under worst case charge sharing conditions. Minimum capacitance and delays are calculated for a transmission gate circuit, and static and dynamic power consumption is solved analytically and graphically. Finally Interconnect properties are explored by computing the resistance, capacitance, and delay for a distributed RC wire.