AhsanAliUet
Enthusiast Electrical Engineer with interest in Embedded Systems, Computer Architecture and SoC.
@ee-uetLahore
Pinned Repositories
Ahsan-Ali-Interests
My interests and some collaborations
cocotb-examples
Some RTL files have been tested using cocotb (Python)
duty-cycle-and-frequency-controlled-signal-using-verilog
We will make a signal in Verilog which will be a variable duty cycle as well as variable frequency signal which is named as pulse. We can refer this signal pulse as a square wave also with variable duty cycle.
home
Repository for the github site
pak-dsp
Application class Digital Signal Processor that can be used in Signal Conditioning and Image Processing applications.
pak-dsp-tinytapeout-08
A simple digital signal processor submitted for manufacturing to Tiny Tapeout 07..
riscof_compliance
This repository contains necassary configurations for running Architecture Compatibilit Tests on RISC-V based processors.
Speaker-Identification-Using-Machine-Learning
spi-protocol
SPI protocol is implemented and simulated successfully in this repository.
uart-application-in-real-time-simulation-emulation-on-fpga
If we run out of input pins on FPGA, we can instantiate receiver of uart in DUT (design under test). Receiver will receive data from PC serially and convert this serial data to parallel data and give it to DUT to use it without hesitation of shortage of input pins.
AhsanAliUet's Repositories
AhsanAliUet/pak-dsp-tinytapeout-08
A simple digital signal processor submitted for manufacturing to Tiny Tapeout 07..
AhsanAliUet/cocotb-examples
Some RTL files have been tested using cocotb (Python)
AhsanAliUet/duty-cycle-and-frequency-controlled-signal-using-verilog
We will make a signal in Verilog which will be a variable duty cycle as well as variable frequency signal which is named as pulse. We can refer this signal pulse as a square wave also with variable duty cycle.
AhsanAliUet/home
Repository for the github site
AhsanAliUet/pak-dsp
Application class Digital Signal Processor that can be used in Signal Conditioning and Image Processing applications.
AhsanAliUet/riscof_compliance
This repository contains necassary configurations for running Architecture Compatibilit Tests on RISC-V based processors.
AhsanAliUet/Speaker-Identification-Using-Machine-Learning
AhsanAliUet/Ahsan-Ali-Interests
My interests and some collaborations
AhsanAliUet/alu-using-only-one-adder
In this repository, an ALU (Arithmetic and logic unit) is made using one full adder which can add as well as subtract using that adder only
AhsanAliUet/cva6
The CORE-V CVA6 is an Application class 6-stage RISC-V CPU capable of booting Linux
AhsanAliUet/gnu-tool-chain-for-riscv-lite
We will use this tool chain to convert our C language codes to machine codes and assembly codes to machine codes for our own made RISC-V processor (Both single cycle and Pipelined).)
AhsanAliUet/hangman-game-in-python
AhsanAliUet/uart-application-in-real-time-simulation-emulation-on-fpga
If we run out of input pins on FPGA, we can instantiate receiver of uart in DUT (design under test). Receiver will receive data from PC serially and convert this serial data to parallel data and give it to DUT to use it without hesitation of shortage of input pins.
AhsanAliUet/block-chain-network
This repository provides basic tools and instructions to setup a network of IBFT nodes for peer to peer energy trading
AhsanAliUet/DeepLearningExamples
State-of-the-Art Deep Learning scripts organized by models - easy to train and deploy with reproducible accuracy and performance on enterprise-grade infrastructure.
AhsanAliUet/electronics-data
This repository contains some temporary data for some of my electronics projects.
AhsanAliUet/github-actions
AhsanAliUet/gtkwave
GTKWave is a fully featured GTK+ based wave viewer for Unix and Win32 which reads LXT, LXT2, VZT, FST, and GHW files as well as standard Verilog VCD/EVCD files and allows their viewing.
AhsanAliUet/migen
A Python toolbox for building complex digital hardware
AhsanAliUet/occamy
A high-efficiency system-on-chip for floating-point compute workloads.
AhsanAliUet/Pak-DSP-Caravel
AhsanAliUet/pak-rv-core
RISC-V based Linux Capable Processor
AhsanAliUet/random-number-generator
Customized Random Number Generator wheel with full frontend and backend.
AhsanAliUet/RISC-V-32I-5-stage-Pipeline-Processor
5 stage pipeline implementation of RISC-V 32I Processor.
AhsanAliUet/riscv-gcc-prebuilt
📦 Prebuilt RISC-V GCC toolchains for x64 Linux.
AhsanAliUet/single-cycle-risc-v-implementation-in-system-verilog-with-verification
Fully implemented single cycle RISC-V with support of R, I, J, S, B and U type instructions. Also, formal verification test benches are written.
AhsanAliUet/Sysnopsis-of-Platform-Level-Interrupt-Controller
AhsanAliUet/tools
This repo contains prebuilt binaries of some tools like verilator, sail_cSim etc.
AhsanAliUet/uart-transmitter-Tx-implementation-in-system-verilog
We have implemented UART (Universal Asynchronous Receiver Transmitter) using System Verilog.
AhsanAliUet/UETRV_ESoC