Implementation of a 4-bit Full Adder circuit in VHDL.
-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
(Copyright (C) 2020 Intel Corporation. All rights reserved).
-Simulation result using ModelSim-Altera contained in Quartus.
-Note: This project uses a testbench to simulate the circuit. The testbench was implemented at the top of the circuit hierarchy.