/Full_Adder

4-bit Full Adder circuit in VHDL

Primary LanguageVHDL

Full Adder

Implementation of a 4-bit Full Adder circuit in VHDL.

Built With

-Quartus Prime Version 20.1.1 Build 720 11/11/2020 SJ Lite Edition
(Copyright (C) 2020 Intel Corporation. All rights reserved).

Circuit Schematic

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Simulation

-Simulation result using ModelSim-Altera contained in Quartus.
-Note: This project uses a testbench to simulate the circuit. The testbench was implemented at the top of the circuit hierarchy.
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