AndreMerendeira

AndreMerendeira's Stars

• IObundle/iob-versat

  Coarse Grained Reconfigurable Array

  Language:C++1912

• IObundle/iob-eth

  Basic Verilog Ethernet core and C driver functions

  Language:Verilog104

• IObundle/py2hwsw

  a Python framework for managing embedded HW/SW projects

  Language:Python93

• IObundle/iob-soc-tester

  System-on-Chip for In-Silicon Verification of IP Cores

  84

• IObundle/iob-soc-opencryptolinux

  Running Linux on IOb-SoC-OpenCryptoHW

  Language:C139

• IObundle/iob-soc-opencryptohw

  Reconfigurable Hardware-Accelerated Open-Source Cryptographic IP Cores

  Language:C1112

• IObundle/iob-cache

  Verilog Configurable Cache

  Language:Verilog16733

• IObundle/iob-soc

  RISC-V System on Chip Template

  Language:Makefile15386

• AndreMerendeira/iob-soc

  RISC-V System on Chip Template Based on the picorv32 Processor

  Language:Python1

• AndreMerendeira/iob-mem

  Verilog behavioral description of various memories

  Language:Verilog1

• IObundle/iob-div

  Verilog Divider Cores

  Language:Verilog33

• IObundle/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog612