Pinned Repositories
duo-de
Surface Duo Dual Experience ( 🍰 AOSP | Android 15 | DUO1 | DUO2 )
FPGA-DepthMap-Basys3
Real Time depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.
FPGA-stereo-Camera-Basys3
Integration of two camera 📷 modules to Basys 3 FPGA
FPGA_depthMap
Using stereo vision 👀 to identify the obstacles by processing images on a FPGA
ice40lib
Peripheral library 📚 for open source FPGAs based on iCE40. (Configured for ICESugar-Nano)
rsa4k
Verilog implementation of RSA 4096
RTK-NTRIP-RTCM
Contains program to Send RTCM3 📡 data to Hosted NTRIP server and fetch NTRIP data and display on another rover. Real time kinematic supported base and rover (Ublox-M8P) GPS units are required.
StopWatch-Basys3
Stopwatch ⏱️ implemented using Verilog with Vivado
sweetRV
sweetRV 🧁 is a SoC with a minimal RISC-V processor with firmware for IceSugar-Nano FPGA
TrafficLightController
Design a sequential circuit (FSM) and implement using Verilog
Archfx's Repositories
Archfx/FPGA-stereo-Camera-Basys3
Integration of two camera 📷 modules to Basys 3 FPGA
Archfx/RTK-NTRIP-RTCM
Contains program to Send RTCM3 📡 data to Hosted NTRIP server and fetch NTRIP data and display on another rover. Real time kinematic supported base and rover (Ublox-M8P) GPS units are required.
Archfx/FPGA-DepthMap-Basys3
Real Time depth map 🏞️ generation using SSD algorithm on low end Basys 3 FPGA. Support 320x240 and 160x120 resolutions.
Archfx/FPGA_depthMap
Using stereo vision 👀 to identify the obstacles by processing images on a FPGA
Archfx/TrafficLightController
Design a sequential circuit (FSM) and implement using Verilog
Archfx/StopWatch-Basys3
Stopwatch ⏱️ implemented using Verilog with Vivado
Archfx/eKema
Machine learning for Paddy cultivation
Archfx/XOR-FPGA
How I inferred XOR neural network on FPGA with 8-bits
Archfx/DIY-PRM_01
Arduino PRM01 module for RadioLink At9 and At10
Archfx/Kobuki-Serial-Controller
Serial raw python implementation for controlling Kobuki Robot base
Archfx/550_DRONE_CAD_PX4
3D model of the Final drone assembly for the Simulation
Archfx/assert_NoC
Assertion based Network on Chip Security Implementation
Archfx/DengAI
Solution to DengAI: Predicting Disease Spread HOSTED BY DRIVENDATA
Archfx/ImageFilters
Alpha trimmed mean filter and Adaptive filter implemented using Scilab
Archfx/REGEN_ESC_VESC
The code for my custom BLDC controller.
Archfx/SnpsTools
Simple beginner tutorial for Synopsys tool chain
Archfx/V2G
Verilog variables descriptions to graphs converting tool
Archfx/Goblin-VTOL
micro sized Vertical takeoff and landing aircraft based on FT Goblin fixed wing
Archfx/iobCache
Archfx/MiniMe
Micro sized Line following robot with arm to grab
Archfx/MultiWii_RF24
Archfx/NOB
NightOfBrethren Augmented Reality mobile application
Archfx/NoCDebug
Archfx/ProNoC
Prototype-network-on-chip (ProNoC) is an EDA tool that facilitates prototyping of custom heterogeneous NoC-based many-core-SoC (MCSoC).
Archfx/ProNoC_MPSoC
Multiprocessor Network on Chip which consists of 4 Mork1x processors
Archfx/RoboCat
Robust and Heavy-Duty Drone Platform 🕹️ (CAD model)
Archfx/SinhalaFilmReviewIndexer
Project for indexing and querying Sinhala news article based terms.
Archfx/Unroll-er
Hardware Description loop Unroll-er for Verification (ex: For used in EBMC etc). Currently support Verilog
Archfx/volte-fix
Fixes Qualcomm VoLTE for DUO-DE
Archfx/YosysFlatten
Flatten RTL hierarchy designs with Yosys