Arvind-Srinivasan

Georgia Tech Grad: B.S. CompE '21; M.S. ECE '23

Apple

Pinned Repositories

Arvind-Srinivasan
GitHub Profile Repository
0 1 00
issuer-icons
Vector graphics of one-time password issuer logo's, used in Raivo OTP for iOS.
Language:Python0 0 00
keychain-pcb
GitHub repository for my entry to the RoboJackets Winter 2020 PCB Competition
0 0 00
Room-Counter
Our HackGT 2020 Project
Language:Python1 0 00
symbiflow-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Language:Jupyter Notebook0 0 00
symbiflow-examples
Example designs showing different ways to use SymbiFlow toolchains.
Language:Verilog0 0 00
Verilog-Projects
A variety of projects using FOSS Verilog tools for the Alchitry CU
Language:Makefile1 1 00
yosys
SymbiFlow WIP changes for Yosys Open SYnthesis Suite
Language:C++0 0 00
f4pga-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Language:Jupyter Notebook273 25 630113
GitHubGraduation-2021
Join the GitHub Graduation Yearbook and "walk the stage" on June 5.
Language:JavaScript1.4k 25 2407.1k

Arvind-Srinivasan/Room-Counter
Our HackGT 2020 Project
Language:Python1 0 00
Arvind-Srinivasan/Verilog-Projects
A variety of projects using FOSS Verilog tools for the Alchitry CU
Language:Makefile1 1 00
Arvind-Srinivasan/Arvind-Srinivasan
GitHub Profile Repository
0 1 00
Arvind-Srinivasan/issuer-icons
Vector graphics of one-time password issuer logo's, used in Raivo OTP for iOS.
Language:Python0 0 00
Arvind-Srinivasan/keychain-pcb
GitHub repository for my entry to the RoboJackets Winter 2020 PCB Competition
0 0 00
Arvind-Srinivasan/symbiflow-arch-defs
FOSS architecture definitions of FPGA hardware useful for doing PnR device generation.
Language:Jupyter Notebook0 0 00
Arvind-Srinivasan/symbiflow-examples
Example designs showing different ways to use SymbiFlow toolchains.
Language:Verilog0 0 00
Arvind-Srinivasan/yosys
SymbiFlow WIP changes for Yosys Open SYnthesis Suite
Language:C++0 0 00