Pinned Repositories
AshmaTabasshumNoshin.github.io
CNN-FPGA
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
Compiler-Lab
Computer-Graphics-Lab
CSE-2100-project
CSE-3100-project-Railway-Website
Digit-Recognition
Developed architecture for convolutional neural network and trained it on MNIST dataset using MATLAB. Implemented the neural network by developing a GUI using C++ which classifies the digit drawn on the screen by the user.
DSP
Image-Classification-using-CNN-on-FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
Implementation-of-Back-Propagation-Algorithm-in-Verilog
AshmaTabasshumNoshin's Repositories
AshmaTabasshumNoshin/AshmaTabasshumNoshin.github.io
AshmaTabasshumNoshin/CNN-FPGA
Implementation of CNN on ZYNQ FPGA to classify handwritten numbers using MNIST database
AshmaTabasshumNoshin/Compiler-Lab
AshmaTabasshumNoshin/Computer-Graphics-Lab
AshmaTabasshumNoshin/CSE-2100-project
AshmaTabasshumNoshin/CSE-3100-project-Railway-Website
AshmaTabasshumNoshin/Digit-Recognition
Developed architecture for convolutional neural network and trained it on MNIST dataset using MATLAB. Implemented the neural network by developing a GUI using C++ which classifies the digit drawn on the screen by the user.
AshmaTabasshumNoshin/DSP
AshmaTabasshumNoshin/Image-Classification-using-CNN-on-FPGA
Project is about designing a Trained Neural Network on FPGA to classify an Image Input using CNN.
AshmaTabasshumNoshin/Implementation-of-Back-Propagation-Algorithm-in-Verilog
AshmaTabasshumNoshin/Library-project
AshmaTabasshumNoshin/RISC-V
An implementation of the RISC-V 32I ISA on an Altera FPGA in Verilog with a cache and process-switching OS
AshmaTabasshumNoshin/RUET-Lab-Works
All my sessional lab codes of RUET life are gathered here :3
AshmaTabasshumNoshin/Verilog
AshmaTabasshumNoshin/Yelp-using-vue.js