AshmaTabasshumNoshin/RISC-V

An implementation of the RISC-V 32I ISA on an Altera FPGA in Verilog with a cache and process-switching OS

RISC-V

• An implementation of a RISC-V 32I ISA, minus FENCE and CSR instructions, plus MUL.
• Implemented on an Altera Cyclone IV FPGA development board in Verilog.
• Implements a watchdog timer, an interrupt handler, and a process-switching OS.
• Includes an 8 line direct-mapping cache.

Here you can view a demonstration of the Process Handling OS running two programs simultaneously: