AurelienUoU

Pinned Repositories

tangxifan-eda-tools
Language:C++10
fifo_to_one_clock_dpram
Testcase for techmapping using Yosys
Language:Verilog00
OpenFPGA
An Open-source FPGA IP Generator
Language:Verilog816160

AurelienUoU's Repositories

AurelienUoU/fifo_to_one_clock_dpram
Testcase for techmapping using Yosys
Language:Verilog
AurelienUoU/tangxifan-eda-tools
Language:C++1