lnis-uofu/OpenFPGA

Issues

• Tileable routing architecture

  #1828 opened 2 months ago by narutozxp
  0

• Getting fanin error while trying to use custom pinlocations

  #1814 opened 2 months ago by PradyumnaG
  1

• Vpr wrapper typo

  #1821 opened 2 months ago by rafljiarui
  0

• New command: report_reference for FPGA fabric modeling

  #1780 opened 3 months ago by tangxifan
  0

• Getting an error regarding route_chan_width

  #1755 opened 3 months ago by PradyumnaG
  1

• ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_and2_MIN_ROUTE_CHAN_WIDTH

  #1752 opened 3 months ago by PradyumnaG
  6

• Does OpenFPGA support global short-wired outputs?

  #1738 opened 3 months ago by yunuseryilmaz18
  4

• Do all parameters in task.conf file work?

  #1749 opened 3 months ago by chengquan
  2

• Bitstream updates and reconfiguration support in OpenFPGA

  #1723 opened 4 months ago by ohault
  1

• ERROR (00_and2_MIN_ROUTE_CHAN_WIDTH) - Failed to execute openfpga flow - 00_and2_MIN_ROUTE_CHAN_WIDTH

  #1721 opened 4 months ago by himanshu1308
  0

• Assertion '1 == driver_switches.size()

  #1710 opened 5 months ago by kpatinos-intel
  1

• 'CHANX == rr_graph.node_type(src_node) || CHANY == rr_graph.node_type(src_node)' failed.

  #1697 opened 5 months ago by kpatinos-intel
  2

• CBx/CBy support input ports from grid outputs

  #1644 opened 5 months ago by tangxifan
  3

• repacker changes internal feedback path to external feedback

  #1671 opened 5 months ago by rs-dhow
  0

• cbx/cby muxes lose inputs if they are on same "index"

  #1668 opened 5 months ago by rs-dhow
  0

• repacker greatly alters one LUT in 2xLUT5 mode of an FLE in some cases when other LUT5 is unused yet configured as a wire-LUT in the .net

  #1672 opened 5 months ago by rs-dhow
  0

• repacker/bitstream generation changes internal block muxing to different IPIN

  #1670 opened 5 months ago by rs-dhow
  0

• repacker seems underconstrained and fully constrained would be simpler and easier to work with

  #1673 opened 5 months ago by rs-dhow
  0

• bitstream generation changes net routing

  #1669 opened 5 months ago by rs-dhow
  0

• Failed to execute openfpga flow - 00_and2_MIN_ROUTE_CHAN_WIDTH

  #1660 opened 6 months ago by Gurusatwik
  0

• Enhancements on write_fabric_hierarchy

  #1635 opened 6 months ago by tangxifan
  2

• cheat code support

  #1643 opened 6 months ago by ThetaX55
  3

• Contributor guide link in README is broken

  #1534 opened 9 months ago by DeflateAwning
  1

• Global ports are connected to GPIOs

  #1553 opened 6 months ago by AhmadHouraniah
  1

• Document seems not correct

  #1539 opened 6 months ago by narutozxp
  1

• Is random fabric key generation the only method for secure user's FPGA IP design?

  #1563 opened 6 months ago by WazaAbdulkadir
  1

• Issue when running 3 ram

  #1572 opened 6 months ago by ducminhnguyen123
  1

• questions about clock_network

  #1571 opened 6 months ago by Chris202305
  1

• the output file which contains the position of macros

  #1575 opened 8 months ago by ducminhnguyen123
  1

• Question about and2_output_verilog.v in full_testbench

  #1585 opened 6 months ago by Lukemagik
  2

• Question about fpga_top.v

  #1586 opened 6 months ago by Lukemagik
  1

• Repack failure for nets with multiple destinations within a complex block.

  #1588 opened 8 months ago by Crossbomber
  1

• Power analysis report

  #1626 opened 6 months ago by Gurusatwik
  1

• Fabric that fits input RTL

  #1642 opened 6 months ago by findnabeel
  1

• How to simulate a large file?

  #1520 opened 6 months ago by ducminhnguyen123
  1

• Generate Fabric for and2 on k6_frac_N10_adder_chain_40nm_openfpga.xml architecture

  #1632 opened 6 months ago by Gurusatwik
  0

• Support waveform output in preconfigured fabric wrapper Verilog

  #1606 opened 6 months ago by tangxifan
  0

• Modelsim simulation shows undefined output for FPGA output lines

  #1629 opened 6 months ago by chaitalisathe
  1

• Output preferred sides of pins for each block in an FPGA fabric w.r.t. architecture definition

  #1615 opened 7 months ago by tangxifan
  0

• Full testbench is not working

  #1528 opened 9 months ago by ducminhnguyen123
  9

• VPR flat_routing support

  #1611 opened 7 months ago by alaindargelas
  2

• Question about BRAM preload data content

  #1507 opened 8 months ago by chungshien
  4

• synthesis timing error

  #1543 opened 9 months ago by anudeepdharavathu
  0

• error when using gpio in skywater130

  #1542 opened 9 months ago by ducminhnguyen123
  0

• how to change flip-flop by flip-flop of skywater130 in xml files

  #1523 opened 9 months ago by ducminhnguyen123
  0

• Maintain backward compatibility for concat_pass_wire

  #1531 opened 9 months ago by alaindargelas
  0

• The config of the server execute openfpga

  #1526 opened 9 months ago by ducminhnguyen123
  0

• different area between 10LUTs and 1LUT

  #1513 opened 10 months ago by ducminhnguyen123
  5

• New Tileable Layout Structure Request

  #1505 opened 9 months ago by msaideroglu
  2

• TSMC lib?

  #1510 opened 10 months ago by zliu1Charlotte
  2