Pinned Repositories
LSOracle
IDEA project source files
OpenFPGA
An Open-source FPGA IP Generator
SOFA
SOFA (Skywater Opensource FPGAs) based on Skywater 130nm PDK and OpenFPGA
awesome-hpmicro
A curated list of HPMicro MCU related code and resources.
caravel
libOpenFPGA
Useful Libraries for OpenFPGA project
micro_benchmark
Micro Benchmarks for FPGA design verification
rabbit-fudan
Automatically exported from code.google.com/p/rabbit-fudan
tangxifan-eda-tools
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
tangxifan's Repositories
tangxifan/tangxifan-eda-tools
tangxifan/libOpenFPGA
Useful Libraries for OpenFPGA project
tangxifan/micro_benchmark
Micro Benchmarks for FPGA design verification
tangxifan/awesome-hpmicro
A curated list of HPMicro MCU related code and resources.
tangxifan/caravel
tangxifan/dspfilters
A collection of demonstration digital filters
tangxifan/hdl-benchmarks
Collection of open HDL modules, subsystems and microprocessors (benchmarks) that are used for related tools testing.
tangxifan/hfill
A speculative polyfill to use the h element in HTML
tangxifan/rabbit-fudan
Automatically exported from code.google.com/p/rabbit-fudan
tangxifan/eduBOS5
A compact, configurable RISC-V core
tangxifan/libargparse
A C++ command-line parsing library
tangxifan/logik
A configurable RTL to bitstream FPGA toolchain
tangxifan/LVDS_Transceiver
tangxifan/OpenFPGA
An Open-source FPGA IP Generator
tangxifan/Publications
tangxifan/pygantt
tangxifan/pyobfuscate
pyobfuscate
tangxifan/ResInsight
3D viewer and post processing of reservoir models
tangxifan/sphinx_doc_template
A template project for Sphinx-based documentation
tangxifan/spydrnet
A flexible framework for analyzing and transforming FPGA netlists. Official repository.
tangxifan/Surelog
SystemVerilog 2017 Pre-processor, Parser, Elaborator, UHDM Compiler. Provides IEEE Design/TB C/C++ VPI and Python AST API. Compiles on Linux gcc, Windows msys2-gcc & msvc, OsX
tangxifan/tcl
The Tcl Core. (Mirror of core.tcl-lang.org)
tangxifan/verilog_spi
A simple Verilog SPI master / slave implementation featuring all 4 modes.
tangxifan/VexRiscv
A FPGA friendly 32 bit RISC-V CPU implementation
tangxifan/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
tangxifan/yosys-bigsim
A collection of big designs to run post-synthesis simulations with yosys
tangxifan/zipcpu
A small, light weight, RISC CPU soft core