/micro_benchmark

Micro Benchmarks for FPGA design verification

Primary LanguageVerilogMIT LicenseMIT

Micro Benchmarks for FPGA design verification

RTL Compatibility RTL Verification Documentation Status

Version: see VERSION.md

Licenses

Most of the benchmarks are in MIT license.

Note

Please note that external benchmarks which may not be in compatible licenses. For each external benchmarks, LICENSE file can be found under its location

The list of external benchmarks is as follows. Please double check before using.

  • interface/opencores_can
  • interface/opencores_gpio
  • interface/opencores_i2c
  • interface/opencores_ptc
  • interface/opencores_spi
  • interface/opencores_simple_spi
  • interface/opencores_uart16550
  • interface/verilog_spi
  • interface/wb_lcd
  • interface/wb_lcd_ramless
  • interface/wb_rs232_syscon
  • interface/wbscope
  • interface/wbqspiflash
  • interface/tiny_spi
  • interface/sockit_owm
  • processors/VexRiscv_full
  • processors/VexRiscv_murax
  • processors/VexRiscv_small
  • dsp/dspfilters
  • dsp/cordic
  • dsp/cordic_core
  • dsp/pid_controller
  • dsp/cr_div
  • dsp/signed_integer_divider

Documentation

Full documentation can be found at here

Benchmarks

Benchmarks are categorized in the following directories, depending their logic functions:

  • dsp: Digital Signal Processing (DSP) -related applications
  • fsm: Finite State Machine (FSM) - related applications
  • interface: system bus and protocols, such as SPI, UART etc.
  • processor: CPU cores
  • ram: Memory blocks, including random access memories, FIFOs, etc.
  • simple_gates: combinational circuits in small sizes
  • simple_registers: sequential circuits in small sizes