tangxifan/hdl-benchmarks

Collection of open HDL modules, subsystems and microprocessors (benchmarks) that are used for related tools testing.

hdl-benchmarks

Collection of HDL modules, subsystems and microprocessors (benchmarks) that are used for related tools testing.

Structure

The project has the following catalog structure:

• bash - Bash scripts directory
• hdl - HDL benchmarks directory
  • iwls05 - IWLS'2005 benchmarks
  • lgsynth91 - LGSynth'1991 benchmarks
  • mcnc - MCNC'91 benchmarks
  • quip - Quartus University Interface Program (QUIP) benchmarks
  • texas97 - Texas-97 benchmarks
  • vcegar - VCEGAR benchmarks
  • verilog2smv - Verilog2SMV benchmarks

Benchmarks

The following public benchmarks are updated (several bugs and formatting issues are fixed) and are used in this project:

• IWLS 2005 benchmarks were collected by Christoph Albrecht, Cadence Research Laboratories at Berkeley in June 2005 for the sake of IWLS conference;

• LGSynth'91 benchmarks (sometimes called as IWLS'91) is a collection of examples used in conjunction with the 1991 Microelectronics Center of North Carolina (MCNC) International Workshop on Logic Synthesis and the extension of the 1989 Logic Synthesis and Optimization Benchmarks User Guide, that were collected by Petr Fišer, Czech Technical University in Prague;

• MCNC benchmarks were published for Microelectronics Center of North Carolina (MCNC) International Workshop on Logic Synthesis, 1991, and were collected by Petr Fišer, Czech Technical University in Prague;

• QUIP benchmarks were developed in Altera (now Intel) company as a part of freely distributed QUIP toolkit;

• Texas-97 Benchmarks were developed at the University of Texas as a part of the formal verification course of Dr. Adnan Aziz;

• VCEGAR Benchmarks were developed at the University of Oxford by the system verification team led by Daniel Kroening as a test suite for the VCEGAR (now EBMC) tool;

• Verilog2SMV Benchmarks were developed at the Bruno Kessler Foundation by a team of researchers as a test suite for the Verilog2SMV tool.

Several benchmarks are included as submodules:

• EPFL benchmarks were developed at École Polytechnique Fédérale de Lausanne and consist of 23 natively combinational circuits designed to challenge modern logic optimization tools. The benchmark suite is divided into arithmetic, random/control and MtM (More than ten Milion gates) parts. Each circuit is distributed in Verilog, VHDL, BLIF and AIGER formats.