Pinned Repositories
OpenFPGA
An Open-source FPGA IP Generator
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
OpenFPGA
An Open-source FPGA IP Generator
Backend
Compiler backend from packing to bitstream generation.
FOEDAG
Framework Open EDA Gui
FOEDAG_rs
Raptor's GUI
Raptor
Raptor end-to-end FPGA Compiler and GUI
yosys_rs
Raptor's Yosys hard fork. Contains optimizations
yosys_verific_rs
Yosys + (Optional) Verific Integration
chungshien's Repositories
chungshien/OpenFPGA
An Open-source FPGA IP Generator
chungshien/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research