chungshien

Pinned Repositories

OpenFPGA
An Open-source FPGA IP Generator
Language:Verilog00
vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language:C++00
OpenFPGA
An Open-source FPGA IP Generator
Language:Verilog813 43 440160
Backend
Compiler backend from packing to bitstream generation.
Language:C++3 5 73
FOEDAG
Framework Open EDA Gui
Language:C++58 17 15230
FOEDAG_rs
Raptor's GUI
Language:C++5 5 74
Raptor
Raptor end-to-end FPGA Compiler and GUI
Language:Verilog58 6 6222
yosys_rs
Raptor's Yosys hard fork. Contains optimizations
Language:C++1 2 64
yosys_verific_rs
Yosys + (Optional) Verific Integration
Language:Verilog4 4 896

chungshien's Repositories

chungshien/OpenFPGA
An Open-source FPGA IP Generator
Language:Verilog00
chungshien/vtr-verilog-to-routing
Verilog to Routing -- Open Source CAD Flow for FPGA Research
Language:C++00