/Cache-Simulation-in-VHDL

This consists of a simulation of direct mapping in cache using VHDL

Primary LanguageVHDL

Cache-Simulation-in-VHDL

This consists of a simulation of direct mapping in cache using VHDL

I have created a cache simulation using the VHDL and simulated the concept of direct Mapping and the Write-through policy using the created cache. ModelSim Simulator was used to simulate the VHDL code. Each block of cache consists of 8-bit word.