Azzam-Alhussain
Ph.D. Candidate | Electrical Engineering | University of Central Florida
University of Central Florida Orlando,FL,USA
Azzam-Alhussain's Stars
midday-ai/midday
Run your business smarter 🪄
huggingface/lerobot
🤗 LeRobot: End-to-end Learning for Real-World Robotics in Pytorch
openxla/xla
A machine learning compiler for GPUs, CPUs, and ML accelerators
ONNC/onnc
Open Neural Network Compiler
OpenDevin/OpenDevin
🐚 OpenDevin: Code Less, Make More
PX4/PX4-Autopilot
PX4 Autopilot Software
NVIDIA-AI-IOT/jetracer
An autonomous AI racecar using NVIDIA Jetson Nano
sharc-lab/DGNN-Booster
sharc-lab/LightningSim
A fast, accurate trace-based simulator for High-Level Synthesis.
CVHub520/X-AnyLabeling
Effortless data labeling with AI support from Segment Anything and other awesome models.
zeroasiccorp/umi
Universal Memory Interface (UMI)
nandland/nandland
All code found on nandland is here. underconstruction.gif
marimo-team/marimo
A reactive notebook for Python — run reproducible experiments, execute as a script, deploy as an app, and version with git.
towardsai/tutorials
AI-related tutorials. Access any of them for free → https://towardsai.net/editorial
xupgit/FPGA-Design-Flow-using-Vivado
This course gives an introduction to digital design tool flow in Xilinx programmable devices using Vivado® Design software suite
Xilinx/kria-vitis-platforms
Kria KV260 Vitis platforms and overlays
HiLab-git/WORD
[MedIA2022]WORD: A large scale dataset, benchmark and clinical applicable study for abdominal organ segmentation from CT image
NVIDIA-AI-IOT/tao-toolkit-triton-apps
Sample app code for deploying TAO Toolkit trained models to Triton
niconielsen32/ComputerVision
snbk001/100DaysofRTL
100DaysofRTL & System Verilog design: basic logic gates, mux, half/full subtractor, Encoder, D flipflop, 8 bit counter, LFSR, Custom Counter, Mux using case, JK flip flop, T flip flop, positive edge detection, Priority encoder, Barrel shifter, Signed Magnitude adder, Free Running Counter, Mod-m Counter, Edge Detector mealy Moore
snbk001/Verilog-Design-Examples
Verilog Design Examples with self checking testbenches. Half Adder, Full Adder, Mux, ALU, D Flip Flop, Sequence Detector using Mealy machine and Moore machine, Number of 1s, Binary to Gray Conversion, Up down counter, Clock Divider, PIPO, n bit universal shift register, 4 bit LFSR, Single port RAM, Dual port RAM, Synchronous FIFO, Asynchronous FIFO, 8x8 Sequential Multiplier
3DTopia/3DTopia
Text-to-3D Generation within 5 Minutes
cyrusbehr/YOLOv8-TensorRT-CPP
YOLOv8 TensorRT C++ Implementation
giranntu/NVIDIA-TensorRT-Tutorial
A tutorial for TensorRT overall pipeline optimization from ONNX, TensorFlow Frozen Graph, pth, UFF, or PyTorch TRT) framework.
KidsWithTokens/Medical-SAM-Adapter
Adapting Segment Anything Model for Medical Image Segmentation
thegeekbong/100DaysofCVCode
An initiative to be able to create and apply the concepts of the vast field of Computer Vision. By the end of this 100 Days of CV code journey, I would like to be able to show rich code containing my applications of the concepts of Computer Vision.
TUM-AVS/edgar_digital_twin
ptoupas/amd-open-hardware-23
This repository provides an FPGA-based solution for executing object detection, focusing specifically on the popular YOLOv5 model architecture.
AlexMontgomerie/fpgaconvnet-model
Performance and resource models for fpgaConvNet: a Streaming-Architecture-based CNN Accelerator.
microsoft/CSWin-Transformer
CSWin Transformer: A General Vision Transformer Backbone with Cross-Shaped, CVPR 2022