BertVerrycken

ASIC design, ex-Movidius, ex-Mythic AI, ex-Axelera AI, Innatera.

ContractorPortugal

Pinned Repositories

BERT
Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)
Language:VHDL8 2 01
fpga3dprint
FPGA for 3D printer
0 1 00
fusesoc
Package manager and build abstraction tool for FPGA/ASIC development
Language:Python1.2k 65 392246
PeakRDL-regblock
Generate SystemVerilog RTL that implements a register block from compiled SystemRDL input.
Language:Python53 16 10442

BertVerrycken's Repositories

BertVerrycken/BERT
Bit-Efficient Replicator Tech for X, Y, Z axis motor control (3D printers)
Language:VHDL8 2 01
BertVerrycken/fpga3dprint
FPGA for 3D printer
0 1 00