CGAL/cgal

CDT_3 - output surface has a hole though input surface does not

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Issue Details

The surface of the CDT of this input PLC has holes, though the input does not have holes.

final_remeshed_no_tri.zip

The input faces are not perfectly coplanar, but we still don't expect holes.

The experiments were made in CGAL lab

Environment

  • CGAL version: master branch 2504f0c

I tried to solve it, could you review it?