CMU-SAFARI/ramulator
A Fast and Extensible DRAM Simulator, with built-in support for modeling many different DRAM technologies including DDRx, LPDDRx, GDDRx, WIOx, HBMx, and various academic proposals. Described in the IEEE CAL 2015 paper by Kim et al. at http://users.ece.cmu.edu/~omutlu/pub/ramulator_dram_simulator-ieee-cal15.pdf
C++MIT
Issues
- 5
- 2
- 0
- 0
GEM5+Ramulator run issue
#49 opened - 4
- 5
timing lookup table typos?
#47 opened - 2
How to set rowpolicy to Closed?
#46 opened - 3
Ramulator runs forever
#45 opened - 0
HBM generation 2
#44 opened - 3
How to simulate RowClone?
#42 opened - 0
Integration of ramulator with multi2sim
#41 opened - 1
How can I get write request callback?
#40 opened - 0
Org Table
#39 opened - 1
completion time and queue hit
#38 opened - 0
Ramulator + ZSim
#36 opened - 0
- 1
Capacity Mismatch for DDR3
#33 opened - 1
- 0
Multicore Usage + Caches
#31 opened - 3
New gem5 patch is generating build error
#30 opened - 1
Questions regarding DDR4.cpp
#29 opened - 0
- 2
column address bit width
#27 opened - 9
- 2
DRAM<T>:::update_timing() code
#25 opened - 4
Don't Support Read/Write Value ?
#24 opened - 0
Timing (cycle) accurate simulation
#23 opened - 8
x86 Gem5/Ramulator Segmentation Fault
#22 opened - 9
- 2
Failed to compile with Gem5
#20 opened - 1
Ramulator for NVMs
#19 opened - 2
Does cache really work?
#18 opened - 1
- 1
0 Value in Simulation Output
#16 opened - 4
Problem with Ramulator.
#15 opened - 0
- 0
- 6
ramulator addressing
#12 opened - 5
- 0
- 1
- 1
- 3
- 11
- 0
- 4
Failure in installing Ramulator
#4 opened - 2
HBM IPC numbers
#2 opened - 16