Chilhhh

beautyeye

BeautyEye is a Java Swing cross-platform look and feel.

e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

G6

Hazard3

3-stage RV32IMACZb* processor with debug

ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

lab1

test

nvdlahw

RTL, Cmodel, and testbench for NVDLA

openc906

OpenXuantie - OpenC906 Core

openc910

OpenXuantie - OpenC910 Core

Chilhhh/beautyeye

BeautyEye is a Java Swing cross-platform look and feel.

Chilhhh/e200_opensource

Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

Chilhhh/Fuxi

Fuxi (伏羲) is a 32-bit pipelined RISC-V processor written in Chisel3.

Chilhhh/G6

Chilhhh/Hazard3

3-stage RV32IMACZb* processor with debug

Chilhhh/ibex

Ibex is a small 32 bit RISC-V CPU core, previously known as zero-riscy.

Chilhhh/lab1

test

Chilhhh/nvdlahw

RTL, Cmodel, and testbench for NVDLA

Chilhhh/openc906

OpenXuantie - OpenC906 Core

Chilhhh/openc910

OpenXuantie - OpenC910 Core

Chilhhh/ridecore

RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

Chilhhh/RISCV_CPU

A FPGA supported RISC-V CPU with 5-stage pipeline implemented in Verilog HDL

Chilhhh/tiny-gpu

A minimal GPU design in Verilog to learn how GPUs work from the ground up

Chilhhh/tree-core-ide

The next generation integrated development environment for processor design and verification. It has multi-hardware language support, open source IP management and easy-to-use rtl simulation toolset.

Chilhhh/verilog-axi

Verilog AXI components for FPGA implementation

Chilhhh/vivado-risc-v

Xilinx Vivado block designs for FPGA RISC-V SoC running Debian Linux distro

Chilhhh/zhangzhouhe.github.io

Chilhhh/zhanzghouhe

Config files for my GitHub profile.

Chilhhh/zhanzghouhe.github.io

Chilhhh/zzh