Chilhhh

Chilhhh's Stars

• GuoYS0010/hello_e906_zcu104

  move e906 on zcu104

  Language:VHDL72

• WangXuan95/USTC-RVSoC

  An FPGA-based RISC-V CPU+SoC with a simple and extensible peripheral bus. 基于FPGA的RISC-V SoC，包含一个RV32I CPU、一个简单可扩展的总线、一些外设。

  Language:SystemVerilog36875

• tunghoang290780/riscv-ml

  Machine Learning project using RISC-V and NVDLA on Linux

  11

• SocialistDalao/UltraMIPS_NSCSCC

  UltraMIPS SoC composed of dual-issue cpu, pipeline Cache and systematic peripheral.

  Language:Verilog12220

• lizhirui/DreamCore

  Language:C++633

• LoveLonelyTime/Bergamot

  An exquisite superscalar RV32GC processor.

  Language:Scala14513

• ridecore/ridecore

  RIDECORE (RIsc-v Dynamic Execution CORE) is an Out-of-Order RISC-V processor written in Verilog HDL.

  Language:Verilog33465

• m4j0rt0m/axi-lite_uart-ipcore

  AXI4-Lite UART IP core

  Language:Verilog10

• j11332/litex-ted-vu13p

  Language:Python22

• alexforencich/verilog-axi

  Verilog AXI components for FPGA implementation

  Language:Verilog1.6k464

• LeiWang1999/ZYNQ-NVDLA

  NVDLA (An Opensource DL Accelerator Framework) implementation on FPGA.

  Language:Verilog31765

• Advanced-Microelectronics-Group/OpenC910_Modified

  commit rtl and build cosim env

  Language:SystemVerilog368

• sudhamshu091/32-Verilog-Mini-Projects

  Implementing 32 Verilog Mini Projects. 32 bit adder, Array Multiplier, Barrel Shifter, Binary Divider 16 by 8, Booth Multiplication, CRC Coding, Carry Select and Carry Look Ahead Adder, Carry Skip and Carry Save Adder, Complex Multiplier, Dice Game, FIFO, Fixed Point Adder and Subtractor, Fixed Point Multiplier and Divider, Floating Point IEEE 754 Addition Subtraction, Floating Point IEEE 754 Division, Floating Point IEEE 754 Multiplication, Fraction Multiplier, High Radix Multiplier, I2C and SPI Protocols, LFSR and CFSR, Logarithm Implementation, Mealy and Moore State Machine Implementation of Sequence Detector, Modified Booth Algorithm, Pipelined Multiplier, Restoring and Non Restoring Division, Sequential Multiplier, Shift and Add Binary Multiplier, Traffic Light Controller, Universal_Shift_Register, BCD Adder, Dual Address RAM and Dual Address ROM

  Language:Verilog604117

• enjoy-digital/litex

  Build your hardware, easily!

  Language:C3.1k582

• Yawei-Ding/ysyx_riscv64_cpu

  Language:C524

• darklife/darkriscv

  opensouce RISC-V cpu core implemented in Verilog from scratch in one night!

  Language:Verilog2.2k291

• SI-RISCV/e200_opensource

  Deprecated, please go to next generation Ultra-Low Power RISC-V Core https://github.com/riscv-mcu/e203_hbirdv2

  Language:Verilog2.6k1k

• openFPGA666/FpgaGuide

  分享FPGA开发知识、优秀文章、学习网站以及开源项目。本项目收集了github中许多FPGA开源项目。

  48356

• apache/doris

  Apache Doris is an easy-to-use, high performance and unified analytics database.

  Language:Java13k3.3k

• Sodawyx/dnsSystem

  A Simple DNS System -- Coursework of Internet Applications

  Language:C195