Chris1116

Chris1116's Stars

• doocs/source-code-hunter

  😱 从源码层面，剖析挖掘互联网行业主流技术的底层实现原理，为广大开发者 “提升技术深度” 提供便利。目前开放 Spring 全家桶，Mybatis、Netty、Dubbo 框架，及 Redis、Tomcat 中间件等

  Language:Java22.6k453334.2k

• williamfiset/Algorithms

  A collection of algorithms and data structures

  Language:Java17.8k4261794.4k

• sb2nov/resume

  Software developer resume in Latex

  Language:TeX5.7k43331.6k

• The-OpenROAD-Project/OpenROAD

  OpenROAD's unified application implementing an RTL-to-GDS Flow. Documentation at https://openroad.readthedocs.io/en/latest/

  Language:Verilog1.8k531.6k622

• tsinghua-fib-lab/GNN-Recommender-Systems

  An index of recommendation algorithms that are based on Graph Neural Networks. (TORS)

  1k182141

• freechipsproject/chisel-bootcamp

  Generator Bootcamp Material: Learn Chisel the Right Way

  Language:Jupyter Notebook1k6685288

• ben-marshall/awesome-open-hardware-verification

  A List of Free and Open Source Hardware Verification Tools and Frameworks

  51842551

• umd-memsys/DRAMsim3

  DRAMsim3: a Cycle-accurate, Thermal-Capable DRAM Simulator

  Language:C++3591242152

• troyguo/awesome-dv

  Awesome ASIC design verification

  28911169

• neelkshah/MIPS-Processor

  5-stage pipelined 32-bit MIPS microprocessor in Verilog

  Language:Verilog1244114

• shawn2000100/10810CS_342301_OperatingSystem

  作業系統

  Language:C++733135

• Muriukidavid/systemc-examples

  A repository for SystemC Learning examples

  Language:C++674048

• gundambox/DIY_OpenMIPS

  實作《自己動手寫CPU》書上的程式碼

  Language:Verilog6010017

• uobdv/Design-Verification

  Course content for the University of Bristol Design Verification course.

  Language:Eiffel513015

• maze1377/pipeline-mips-verilog

  A classic 5-stage pipeline MIPS 32-bit processor. solve every hazard with stall

  Language:Verilog42228

• lerogo/5-stage-pipeline-cpu

  实现了5段流水的CPU This project is verilog that implements 5-stage-pipeline-cpu

  Language:Verilog34106

• derek8955/ic_contest

  IC Contest

  Language:Verilog339

• XDEv11/ICLAB-2022-FALL

  Language:Verilog33102

• skyzh/mips-cpu

  💻 A 5-stage pipeline MIPS CPU implementation in Verilog.

  Language:Verilog28214

• zli87/Wishbone-to-I2C-bus-controller-IP-Verification

  ASIC Verification at 2022 Spring. This course only use SystemVerilog, did not use UVM.

  Language:VHDL18207

• The-OpenROAD-Project/OpenLane-MPW-CI

  Language:Shell164105

• jiru1997/UVM-examples-and-source-code

  uvm examples and source code

  Language:HTML8103

• WheatBeer/play_with_dramsim3

  MEMORY CENTRIC SYSTEMS FOR AI(CSI6207-01) Lecture at Yonsei(20-1)

  Language:TeX7311

• arpit306/5-Stage-Pipelined-MIPS32-RISC-Processor-Design-on-Verilog

  This repository contains the details and the code for the MIPS32 ISA based RISC Processor, which is implemented in 5 stage pipelined configuration.

  Language:Verilog6102

• usman1515/SystemVerilog-for-Design-and-Verification

  Language:SystemVerilog5100

• pha123661/Five-Stage-RISC-V-Pipeline-Processor-Verilog

  A Verilog implementation of a 5-stage pipeline RISC-V processor.

  Language:Verilog4100

• alvin870203/nthu-verilog-19s

  邏輯設計實驗 | Logic Design Lab | NTHU | 馬席彬教授 | 2019 Spring

  Language:HTML3100

• leesou/PKU-Operating-System

  PKU Operating System Course Materials

  Language:C++3110

• HasiniReddy57/Canny-edge-Detection

  The project Canny Edge Detector is designed as an embedded system model in SystemC suitable for SoC implementation.

  Language:C++110

• jtchen0528/NTHU-EE39800

  Language:C1100