DECA FPGA

Cores development for the DECA FPGA board built around the Altera MAX 10 FPGA.

Pinned Repositories

Arcade_Galaga
Galaga Arcade Core
Language:VHDL8 1 04
BBC_DemiSTify
BBC micro - Demistified for Deca & Neptuno. [This fork is only a mirror, not for development]
Language:VHDL1 0 01
BrianHG-DDR3-Controller
DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. [This fork is only a mirror, not for development]
Language:SystemVerilog4 0 01
DECA_binaries
sof & svf binaries of Arcades, Computers & Consoles cores for DECA board
2 1 00
DECA_board
Documentation and tools related to DECA FPGA board
Language:Python21 3 09
freedom-e300
SiFive's Freedom e300 for the DECA Max10 FPGA
Language:Verilog4 2 02
MemTest
MemTest for SDRAM Mister modules
Language:VHDL1 2 01
NES
NES core
Language:VHDL2 1 00
usb_system
SpinalHDL USB system for the ULPI based Arrow DECA board
Language:Assembly1 1 00
vexriscv_ocd_blog
Repo that shows how to use the VexRiscv with OpenOCD and semihosting.
Language:Assembly1 1 00

DECA FPGA's Repositories

DECAfpga/DECA_board
Documentation and tools related to DECA FPGA board
Language:Python21 3 09
DECAfpga/Arcade_Galaga
Galaga Arcade Core
Language:VHDL8 1 04
DECAfpga/BrianHG-DDR3-Controller
DDR3 Controller, 16 read, 16 write ports, configurable widths, priority, auto-burst size & smart cache for each port. Fully documented source code. TestBenches included. [This fork is only a mirror, not for development]
Language:SystemVerilog4 0 01
DECAfpga/DECA_binaries
sof & svf binaries of Arcades, Computers & Consoles cores for DECA board
2 1 00
DECAfpga/NES
NES core
Language:VHDL2 1 00
DECAfpga/FpgaRiscV
VexRiscv cpu on FPGA. [This fork is only a mirror, not for development]
Language:Verilog1 1 0
DECAfpga/MemTest
MemTest for SDRAM Mister modules
Language:VHDL1 2 01
DECAfpga/sdram_sram_v1.3_mister
Dual 32 MB SDRAM + 2 MB SRAM MiSTer module with 3 extra pins for DECA retro cape 2
1 0 00
DECAfpga/.github
1 0
DECAfpga/apple2efpga
FPGA implementation of an Apple//e (enhanced) - Demistified for Deca, Neptuno and Uareloaded. [This fork is only a mirror, not for development]
Language:GLSL0 01
DECAfpga/archimedes
Acorn Archimedes core DeMiSTified, ported to TC64 and de10lite
Language:Assembly0 0
DECAfpga/c64_DeMiSTify
c64 demistified core. Audio I2S on i2s branch
Language:VHDL0 0
DECAfpga/deca-mandelbrot
The Terasic DECA board as a mandelbrot accelerator. [This fork is only a mirror, not for development]
Language:Python0 0
DECAfpga/DECA_board_test
Deca board test project
Language:Verilog1 0
DECAfpga/DECA_retro_cape_2
Retro cape (addon) for DECA FPGA
Language:HTML0 0
DECAfpga/ep_DeMiSTify
Elan Enterprise FPGA implementation
Language:VHDL0 0
DECAfpga/FlappyBird
Flappy Bird core for MiSTer, MiST, DeMiSTify, Xilinx, GoWin, ...
Language:Verilog0 0
DECAfpga/gameboy
Nintendo Gameboy core - DeMiSTified for Deca, NeptUNO and Unamiga Reloaded
Language:Assembly0 03
DECAfpga/jtbin
Binary files for MiSTerFPGA, Pocket and other platforms
Language:Arc0 0
DECAfpga/Mist_FPGA
Language:VHDL0 01
DECAfpga/MSX1
MSX1 core
Language:VHDL1 02
DECAfpga/NeoGeo_FPGA
NeoGeo FPGA
Language:VHDL0 0
DECAfpga/NES_Demistify
NES core deMiSTified
Language:Assembly0 01
DECAfpga/Next186
Next186 core
Language:Verilog1 01
DECAfpga/Next186_mist
Language:VHDL0 0
DECAfpga/Oric_Mist_48K
Oric Atmos Mist core
Language:VHDL0 0
DECAfpga/PCXT_DeMiSTify
PCXT deMiSTified
Language:Verilog0 0
DECAfpga/SDRAMStressTest
Uses the SDRAM controller from TurboGrafx16 to give an SDRAM chip a heavy workout.
Language:Assembly0 04
DECAfpga/TatungEinstein_DeMiSTify
Demistification of Tatung Einstein micro computer
Language:VHDL0 01
DECAfpga/VIC20_MiST
VIC-20 for MiST & DeMiSTified for Deca and others. See README.md in board folder
Language:Assembly0 0