DOOKNET

但行好事，莫问前程

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Pinned Repositories

2017_10_30_PWM
Control steering engine
Language:Verilog00
2019_8_14_MemoryInit
initial a memory
Language:Verilog00
AM
AM调制解调的FPGA实现
Language:Verilog3 1 00
DDS
sin make square
Language:Verilog0 1 00
Digital_Clock
基于FPGA的数字时钟（Modelsim仿真）
Language:Verilog18 1 05
FFT_IP_Core
Fast Fourier Transform v9.0
Language:Verilog51
FIFO_IP_Core
use FIFO and uart
Language:Verilog1 1 01
Freq_Measure
等精度测频的FPGA实现
Language:Verilog10
Pingpang_RAM
use RAM(true Dual-RAM) to Pingpang
Language:Verilog61
ssr_Ubuntu
Linux下科学上网工具
1 1 00

DOOKNET's Repositories

DOOKNET/Digital_Clock
基于FPGA的数字时钟（Modelsim仿真）
Language:Verilog18 1 05
DOOKNET/Pingpang_RAM
use RAM(true Dual-RAM) to Pingpang
Language:Verilog61
DOOKNET/FFT_IP_Core
Fast Fourier Transform v9.0
Language:Verilog51
DOOKNET/AM
AM调制解调的FPGA实现
Language:Verilog3 1 00
DOOKNET/FIFO_IP_Core
use FIFO and uart
Language:Verilog1 1 01
DOOKNET/Freq_Measure
等精度测频的FPGA实现
Language:Verilog10
DOOKNET/ssr_Ubuntu
Linux下科学上网工具
1 1 00
DOOKNET/2017_10_30_PWM
Control steering engine
Language:Verilog00
DOOKNET/2019_8_14_MemoryInit
initial a memory
Language:Verilog00
DOOKNET/DDS
sin make square
Language:Verilog0 1 00
DOOKNET/DOOKNET.github.io
博客地址：https://DOOKNET.github.io
Language:CSS1 1
DOOKNET/EveryDaySport
从今天开始做一个健康的程序员。
1 0
DOOKNET/FFT_FIFO_UART
Language:Verilog
DOOKNET/FSM
detect '0101'
Language:Verilog
DOOKNET/Pictures_Bed
图床
1 8
DOOKNET/TestBeach_Wave
create wave for testbeach
Language:MATLAB
DOOKNET/WS2812
WS2812 controlled by FPGA
Language:Verilog1 0
DOOKNET/WS2812_Vivado
Based on Vivado 16.4 and it's just a simulation version.
Language:Verilog